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AXI write strobes

jameskim jameskim
Note: This was originally posted on 21st February 2007 at http://forums.arm.com

the AXI spec says:

10.1 About unaligned transfers
[...]
For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be accessed do not align with the natural data width boundary. For example, a 32-bit (four-byte) data packet that starts at a byte address of 0x1002 is not aligned to a 32-bit boundary.


and then shows some examples of bursts with unaligned first bytes.

i also see references to disabling all strobes on any beat of a burst write.

but, what about unaligned ending bytes?  for example, a burst of 1kB starting at address 0x1 would have both an unaligned starting and ending byte.  is this allowed?

do the bytes of a burst have to be contiguous?  could the writes strobes have holes in them, for example, 0x5, 0xa, 0x9, etc.?

also, i was wondering what AXI masters ARM has that makes use of this feature?  do ARM processors ever generate unaligned bursts for instruction or data accesses, or is it only the DMA controller that issues unaligned bursts?  and in what scenario would a master disable all the strobes after starting a burst write (something like interrupting a dirty line castout?)?

thanks!
james
  • 0
    Note: This was originally posted on 21st February 2007 at http://forums.arm.com

    as a follow on, from the AXI spec:

    4.4.3 Wrapping burst
    [...] Two restrictions apply to wrapping bursts:
    "¢ the start address must be aligned to the size of the transfer


    for wrapping bursts, there's an address alignment requirement, but could you use strobes to make it unaligned even though the address is aligned?
  • 0
    Note: This was originally posted on 23rd March 2007 at http://forums.arm.com

    The important word here is CAN. The AWADDR and AWSIZE signals tell you the range of byte lanes that CAN be used, but the WSTRB bits would say which specific possible byte lanes ARE being used in each beat of the FIXED burst.


    thanks for all the responses.

    one more question, it seems that the strobes can start with a byte somewhere after the byte address specified in AWADDR.  can i assume that it would be a violation for the strobe to enable a byte before AWADDR?

    for example, if the address is 0x1, can i assume that a strobe of 0xff would be illegal on the first beat of a burst (assuming 64-bit bus)?
  • 0
    Note: This was originally posted on 27th February 2007 at http://forums.arm.com

    Hi James,

    >but, what about unaligned ending bytes? 

    Wouldn't be allowed. It is only the first transfer in a burst that is unaligned, all the remaining transfers are aligned.

    However for a write transaction you could use the WSTRB bits to signal which of the final bytes is valid, that way having the same effect as an unaligned final transfer in the burst. But you cannot do this for reads.

    > for example, a burst of 1kB starting at address 0x1 would
    > have both an unaligned starting and ending byte.  is this allowed?

    No. The final transfer would be aligned.

    > do the bytes of a burst have to be contiguous?  could the writes
    >  strobes have holes in them, for example, 0x5, 0xa, 0x9, etc.?

    The write strobes can change for each transfer of a burst, so you could see the above sequence.

    > also, i was wondering what AXI masters ARM has that makes
    > use of this feature?

    I am not aware of any current ARM masters that use the WSTRBs to indicate sparse transfers, but maybe someone else will know more about specific ARM master designs.

    Colin.
  • 0
    Note: This was originally posted on 27th February 2007 at http://forums.arm.com

    as a follow on, from the AXI spec:

    4.4.3 Wrapping burst
    [...] Two restrictions apply to wrapping bursts:
    "¢ the start address must be aligned to the size of the transfer


    for wrapping bursts, there's an address alignment requirement, but could you use strobes to make it unaligned even though the address is aligned?


    Hi James,

    Look at section 9.3 where it states "In a fixed burst, the address remains constant, and the byte lanes that CAN be used also remain constant".

    The important word here is CAN. The AWADDR and AWSIZE signals tell you the range of byte lanes that CAN be used, but the WSTRB bits would say which specific possible byte lanes ARE being used in each beat of the FIXED burst.

    So WSTRB could be used to make the FIXED burst appear to be unaligned (even though the AWADDR value actually IS aligned.

    Colin.
  • 0
    Note: This was originally posted on 26th March 2007 at http://forums.arm.com

    The important word here is CAN. The AWADDR and AWSIZE signals tell you the range of byte lanes that CAN be used, but the WSTRB bits would say which specific possible byte lanes ARE being used in each beat of the FIXED burst.


    thanks for all the responses.

    one more question, it seems that the strobes can start with a byte somewhere after the byte address specified in AWADDR.  can i assume that it would be a violation for the strobe to enable a byte before AWADDR?

    for example, if the address is 0x1, can i assume that a strobe of 0xff would be illegal on the first beat of a burst (assuming 64-bit bus)?



    Hi James,

    Yes.

    A start address of 0x1 means that you can use any of the byte lanes WSTRB[7:1] on the 64 bit data bus (assuming AWSIZE indicated a 64 bit transfer), but not WSTRB[0].

    Obviously if AWSIZE indicated a 32 bit transfer, even with a bus width of 64 bits we could only use WSTRB[3:1] for this transfer to AWADDR=0x1.

    Regards,

    Colin
  • 0
    Note: This was originally posted on 28th February 2007 at http://forums.arm.com

    > do the bytes of a burst have to be contiguous?  could the writes
    >  strobes have holes in them, for example, 0x5, 0xa, 0x9, etc.?

    The write strobes can change for each transfer of a burst, so you could see the above sequence.

    > also, i was wondering what AXI masters ARM has that makes
    > use of this feature?

    I am not aware of any current ARM masters that use the WSTRBs to indicate sparse transfers, but maybe someone else will know more about specific ARM master designs.


    I know that, at least, ARM11-MPCore processeur and L220 Level 2 cache controller use sparse strobes. This is due to the fact that they use a merging write buffer. If the application writes several bytes at address 0x0, 0x3, 0x4, the write buffer will be drained using a 64-bit transfer, and strobes will be 0b00011001 and the AXI slave must only update the bytes that are enabled.