CMSIS 6.0.0
__IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
CMSIS 5.9.0
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
it messes up the DFPs..
It looks like this is from the "core_cm3.h" file.
The Abbreviation "IPR" matches the Abbreviation in the Cortex-M3 Devices Generic User Guide
https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/nested-vectored-interrupt-controller/interrupt-priority-registers
Which DFP Is this messing up?