CMSIS 6.0.0
__IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
CMSIS 5.9.0
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
it messes up the DFPs..
Which DFP does not work with CMSIS 6? The C source and header files in DFPs should use the inline functions (e.g. __NVIC_SetPriority) rather than the direct register name. I quickly searched over my installed DFPs and none of them used the IP register.
It looks like this is from the "core_cm3.h" file.
The Abbreviation "IPR" matches the Abbreviation in the Cortex-M3 Devices Generic User Guide
https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/nested-vectored-interrupt-controller/interrupt-priority-registers
Which DFP Is this messing up?
I just saw that this is one of the breaking changes in CMSIS 6. Please see:
https://arm-software.github.io/CMSIS_6/main/Core/core_revisionHistory.html#core6_changes
This discussion might help as well:
github.com/.../122