SPI Master Slave Communication

Are you sure that the Master's MOSI is connected to Slave's MISO, etc? (double-check it).

I do not know about AD, but for the SILabs uCs hardware SPI engines you connect MOSI to MOSI and MISO to MISO. That makes sense to me.

Erik

MOSI = Master OUT, Slave IN (Master to Slave data direction)
MISO = Master IN, Slave OUT (Slave to Master data direction)

So unless the SILabs uCs have some sort of software control on the data direction, I'm guessing you might be mistaken.

Oh, I get it ... sorry!
Yes. Erik. You are right. Thats what I meant.

The point is to make sure that the data direction is correct.

I have properly connected Masters MOSI, MISO, SS and SCLK to corresponding lines of Slave. I have also checked the clock on scope. The master (ADuC814) generates clock properly as per the program logic. Even SS pin is low throughout. Bt still no communication happens btween them.
I changed the slave to ADuC814(earlier ADuC841), and made master transmit the data 2 slave and slave does UART o/p. This works absolutely fine. Here both master and slave operated at same core clock 16.67MHz.Then I changed the slave core clk to 8.3 MHZ, keeping master at 16.67MHz. This time some blanks appeared in between the output (I chkd on HyperTerminal). Don't know why?? Got 2 figure it out. But still I got some output on HT.
However with ADuC841 as slave and slave is made to transmit the data to master(ADuC814), though I am able to see the SCLK that master generates, the MISO line of slave remains high always. Always blanks get printed on HT. This is what I am not able to get it?? The slave core clock is 11.0592Mz and master operates at 16.67MHz.
Could there be some synchronization problem like rising edge of master and slave might be different due to different core clock??

There shouldn't be a problem that master and slave has different processor clocks. However, the slave normally has a limit on the SPI clock speed, i.e. that the processor clock (or device clock) must be n times higher than the SPI clock signal, to make sure that the SPI slave logic runs at enough speed to be able to react. Some processor may require that the SPI slave logic runs at 12 times the SPI clock but this number can vary from processor to processor.

I changed the one slave to ADuC814(earlier ADuC841), and made master transmit the data 2 two slave

how many slaves?

that is important to know

Erik

Although this might not be what your problem is, you might as well eliminate it as a potential source...

You said "Even SS pin is low throughout" so does that mean it is always low like it is shown in your 'master' code?

I recommend that you insert the SS appropriately between byte transfers. The data-sheet on the ADuC814 indicates that the SS line should be low 'during the byte communication.' (The implication being that it was and/or should return to high otherwise).

If there is a timing issue, the SS line might be used to reset (or re-initialize) the internal state-machine associated with the bit-level transfers.

#include <ADUC814.H>
unsigned char Data[20]; //Store SPI Rx data in Memory
void Uart_Tx(unsigned char AsciData); //Serial Tx
sbit SS = 0xB5;
void main()
{
  char i;
  PLLCON = 0x00; //Core Clk = 16.6777MHz
 //////////baud 0f 4800////////
  RCAP2H = -1; RCAP2L = 0x92;
  TH2 = -1;    TL2 = 0x92;
  SCON = 0x50; T2CON = 0x34;
 //////////////////////////////

  CFG814 = 0x01; // Enable P3.5,6,7 for SPI
  SPICON = 0x37; // Master, CPOH=1,CPOL=0
  SS = 1; // Slave Select Disable // <===== Alter to 1
  for(i=0;i<20;i++)
  {
    SS = 0; // Slave Select Enable // <===== ADD
    SPIDAT = 0x00; // SPI Clock Generate
    while(!ISPI); ISPI = 0;
    SS = 1; // Slave Select Disable// <===== ADD
    Data[i] = (unsigned char)SPIDAT;
  }

 /////////Serial Tx SPI Data into UART//////////
  for(i=0;i<20;i++)
  { Uart_Tx(Data[i]); Uart_Tx('\n'); }
 /////////////////////////////////////////////
}