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SPI Master Slave Communication

Jaydeep Krishna

I am into a project where I need 2 establish communication between ADuc814(Master) and ADuc841(Slave). Master shud Receive data transmitted by Slave. I am unable to establish the comm. I feel there is no response 4rm slave as though master generates the clock and SS pin is low, slave does not response.
Is it necessary that both master and slave should operate in same CLOCK??
For Hardware connection, MOSI, MISO, SCLK and SS pins of Master and Slave are connected.
Foll is the code
Master Code

#include <ADUC814.H>
unsigned char Data[20]; //Store SPI Rx data in Memory
void Uart_Tx(unsigned char AsciData); //Serial Tx
sbit SS = 0xB5;
void main()
{
  char i;
  PLLCON = 0x00; //Core Clk = 16.6777MHz
 //////////baud 0f 4800////////
  RCAP2H = -1; RCAP2L = 0x92;
  TH2 = -1;    TL2 = 0x92;
  SCON = 0x50; T2CON = 0x34;
 //////////////////////////////

  CFG814 = 0x01; // Enable P3.5,6,7 for SPI
  SPICON = 0x37; // Master, CPOH=1,CPOL=0
  SS = 0; // Slave Select Enable
  for(i=0;i<20;i++)
  { SPIDAT = 0x00; // SPI Clock Generate
    while(!ISPI); ISPI = 0;
    Data[i] = (unsigned char)SPIDAT;
  }

 /////////Serial Tx SPI Data into UART//////////
  for(i=0;i<20;i++)
  { Uart_Tx(Data[i]); Uart_Tx('\n'); }
 /////////////////////////////////////////////
}

Slave Code, ADuC841

void main()
{ char i;
  SPICON = 0x24; // Slave, CPOH=1, CPOL=0
  for(i=0;i<20;i++)
  { SPIDAT = 0x38; /*Transmit Dummy Data, Asci of '8'
    while(!ISPI); ISPI = 0; }

}


Friendzzzz Please Help.........

Parents
  • 0 in reply to Jaydeep Krishna

    There shouldn't be a problem that master and slave has different processor clocks. However, the slave normally has a limit on the SPI clock speed, i.e. that the processor clock (or device clock) must be n times higher than the SPI clock signal, to make sure that the SPI slave logic runs at enough speed to be able to react. Some processor may require that the SPI slave logic runs at 12 times the SPI clock but this number can vary from processor to processor.

Reply
  • 0 in reply to Jaydeep Krishna

    There shouldn't be a problem that master and slave has different processor clocks. However, the slave normally has a limit on the SPI clock speed, i.e. that the processor clock (or device clock) must be n times higher than the SPI clock signal, to make sure that the SPI slave logic runs at enough speed to be able to react. Some processor may require that the SPI slave logic runs at 12 times the SPI clock but this number can vary from processor to processor.

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