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What kind of firmware need to copy L2 boot to I-RAM ?

ele

Dear All,

I'm trying to understand a system which is separated by I-RAM and D-RAM as the below,

community.arm.com/.../pastedimage1514364784286v3.png

I want to know what kind of firmware-works things need to copy L2 boot to I-RAM ? what does it purpose for? even I want to know how I-code and D-code work in Cortex M3 in point of view in Memory and Linker Scripts in especially kind of separated I and D cache architecture?

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    The CM3 doesn't have a cache.

    You should review the Reference Manual for the chip being used to understand the vendors implementation.

    Different SRAM will exist at different memory locations, review the memory map and bus matrix for the part in question, and use the scatter file to drive the linker's placement of code and data.

    Code may also be "memcpy"'d to different locations.

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    The CM3 doesn't have a cache.

    You should review the Reference Manual for the chip being used to understand the vendors implementation.

    Different SRAM will exist at different memory locations, review the memory map and bus matrix for the part in question, and use the scatter file to drive the linker's placement of code and data.

    Code may also be "memcpy"'d to different locations.

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