CMSIS message order for an I2C WriteRead transaction

What is the expected timing of events concerning CMSIS I2C events for a Write Read transaction? I am currently using a STM32F407 MCU with the CMSIS library and am surprised by the timing of when the events I an seeing.

Below is a listing of what I see with the latest CMSIS lib from ST/ARM which is installed through the Packs installer in Keil uVision. The library header contains:

 * Copyright (c) 2013-2016 ARM Ltd.
 * $Date:        30. May 2016
 * $Revision:    V2.6
 * Driver:       Driver_I2C1, Driver_I2C2, Driver_I2C3
 * Configured:   via RTE_Device.h configuration file
 * Project:      I2C Driver for ST STM32F4xx

DUT is the STM32F407 and the I2C driver on the DUT is configured as a slave.
An external master I2C issues a WriteRead type of command using the restart condition. A single byte is written to the DUT and 4 bytes are read from it. The order of I2C bus events as observed in a test with the DUT:

1) Master issues [START] condition.
2) Master writes DUT address (7-bit) with write bit set.
3) DUT issues ACK
- CMSIS lib in the DUT issues the "ARM_I2C_EVENT_SLAVE_RECEIVE" event.
4) Master transmits a single byte.
5) DUT issues ACK
6) Master issues [RESTART] condition
7) Master sends out DUT address with read bit set.
8) DUT issues ACK
- CMSIS driver in DUT issues "ARM_I2C_EVENT_TRANSFER_DONE" event.
9) DUT transmits 3 bytes and master issues ACK for each.
- CMSIS driver in DUT issues "ARM_I2C_EVENT_SLAVE_TRANSMIT".
10) DUT transmits 1 byte and master issues NACK (in accordance with the I2C spec).
- CMSIS driver in DUT issues "ARM_I2C_EVENT_TRANSFER_DONE".
11) Master issues [STOP]

What I expect is the following (differences marked with ***):

1) Master issues [START] condition.
2) Master writes DUT address (7-bit) with write bit set.
3) DUT issues ACK
- CMSIS lib in the DUT issues the "ARM_I2C_EVENT_SLAVE_RECEIVE" event.
4) Master transmits a single byte.
5) DUT issues ACK
6) Master issues [RESTART] condition
*** CMSIS driver in DUT issues "ARM_I2C_EVENT_TRANSFER_DONE" event.
7) Master sends out DUT address with read bit set.
8) DUT issues ACK
*** CMSIS driver in DUT issues "ARM_I2C_EVENT_SLAVE_TRANSMIT".
9) DUT transmits 3 bytes and master issues ACK for each.
10) DUT transmits 1 byte and master issues NACK (in accordance with the I2C spec).
- CMSIS driver in DUT issues "ARM_I2C_EVENT_TRANSFER_DONE".
11) Master issues [STOP]

What is the correct way? ALso, is there a document which I can reference which links the bus-events to the ARM_I2C_EVENT_X? I find the CMSIS Doxygen docs from ARM lacking in description of timing events like this. A diagram would be hugely beneficial.

Cheers,
Dirk