I was reading up on the flash eeprom and best I can tell for the stm32f chips this is needed. micromouseusa.com/
Has Keil mdk5 not provided a simple function?
So, if you have a chip without it, you're either going to have to add it externally or emulate it in Flash.
Or is battery backup an option for you?
ST have an App Note on emulating EEPROM in STM32 Flash - but note that their supplied linker script is fundamentally flawed (it doesn't tell the linker that some flash is being used for the EEPROM emulation).
Yes, it gets complicated because of wear-levelling and coping with erasing & re-writing the data in Flash.
Other manufacturers have similar App Notes - you might also be able to get ideas from them...
Sorry I was not clear on that.
I have a st32f205 with eeprom on the chip, I simply just want to write and read form it. This "emulating EEPROM" is confusing me. Is there no easy way to write/read to eeprom on the chip. All the info I find talks about this "emulating EEPROM" when searching for how to use the eeprom.
There is no EEPROM in the part, only FLASH
FLASH is trivial to read, it is within the processors address space.
The FLASH is a mix of 16KB, 64K and 128KB sectors, which are the minimal erase unit. Writing is slow, and requires you to enable programming before writing words of data, you can't write the same word more than once.
Process isn't more complicated than programming a NOR FLASH from the 1990's, you can actual execute while writing, but this will stall the processor with wait-states. Programming and Execution will be faster if the code/data is held in RAM
>>Genuine EEPROM seems rare on Cortex-M microcontrollers
Assume an incompatible/non-optimal mix of process technology.
QUOTE: Yes, it gets complicated because of wear-levelling and coping with erasing & re-writing the data in Flash.
It might be necessary to consider wear-levelling, but even that is not a particularly complicated thing to do. Why do some people try to make everything sound difficult?
Difficult is a relative term. It sadly depends on experience. Flashing anything out side a tool will be difficult for us. In this case even more so because there are not specific chip examples.
SO, apparently that is the case. We specifically budgeted for eeprom. Somehow this was over looked. Now emulation is our only option. It is hard enough to write code with a eeporm viewer and eeprom read and write commands, no we really have work cut out.
So I see the only option is to dedicate a section of code for an eeprom effect. This will certainly work but I'm going to need a good write up to understand this. Processor stalls are fine, we only need to write a few bytes to tell the device how to operate. The plan is to send a USB control transfer to a report ID and tell the chip write bytes here. Then the device can read these values on boot up to know what to do. The problem will be the understanding; Where can I write safely, how can I write, how can I read. The max I would need is 16 bytes.
I would avoid the EEPROM Emulation completely if all you want to do is save a configuration structure.
Pick one (or two) of the early 16KB sectors (@ 0x08004000, 0x08008000 or 0x0800C000), and then journal the writing of your structure across this space, selecting the last one written, and writing the new/changed one beyond the current.
Reading, it's in the address space, so create a structure pointer to the base of the sector and index into them. Have the first word of your structure be a signature, ie not 0xFFFFFFFF and the last word a CRC or checksum to prove/confirm validity.
Simplified method,
typedef struct _CONFIG { uint32_t Signature; // 0x12345678 ? // .. other neat stuff uint32_t Checksum; } CONFIG; CONFIG *config = (CONFIG *)0x08004000; // Config FLASH Sector Base CONFIG curr; const CONFIG default = { 0 }; // Add int i; i = 0; while(config[i+1].Signature != 0xFFFFFFFF) // Index to last i++; if (config[i].Signature == 0xFFFFFFFF) // Empty case { puts("Config Empty, using defaults"); memcpy(&curr, &default, sizeof(CONFIG)); } else { // Check signature and checksum puts("Loading Config"); memcpy(&curr, &config[i], sizeof(CONFIG)); // .. } // ... // Writing next block if (config[i].Signature != 0xFFFFFFFF) // Advance to blank i++; curr.Signature = 0x12345678; // Checksum new configuration, then write to FLASH curr.Checksum = CRC32(0xFFFFFFFF, &curr, sizeof(CONFIG) - 4); FLASH_WriteBlock((uint32_t)&config[i], &curr, sizeof(CONFIG)); // Addr, Buffer, Size
That's not really "avoiding EEPROM emulation completely". That is, for all practical intents and purposes, EEPROM emulation (although a somewhat coarse one).
I see 1 reference to EEPROM in the STM32F20xxx manual. It this what you are talking about using?
Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F20x devices includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Its main features are the following: • Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 day of the month. • Programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. • It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal lowpower RC oscillator or the high-speed external clock divided by 128. The internal lowspeed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. • Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. • A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The 4-Kbyte backup SRAM is an EEPROM-like area.It can be used to store data which need to be retained in VBAT and standby mode.This memory area is disabled to minimize power consumption (see Section 3.18: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.18: Low-power modes). Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or the VBAT pin.
It does avoid pretending it is EEPROM and treats it like FLASH, so it does dispense with a rather thick abstraction from ST with an Adddress/Byte storage system that immediately reduces the available space by at least a quarter.
The problem with pretending is that you keep doing things which are inappropriate rather than change the paradigm to a more appropriate one. ie a FLASH within the MPU address space, vs a I2C EEPROM
Bit weaselly, the data sheet doesn't talk about EEPROM. Must have been losing sails* because the keyword "EEPROM" wasn't hitting on the parametric search.
EEPROM doesn't need batteries, ST has an emulation library using FLASH.
The NVRAM/BKPRAM is within the MPU address space, if the OP has a battery and is comfortable with using that, then map a structure within the NVRAM, copy stuff in/out, or add it to a scatter file.
*beats detector
Yes that may have been the section that game us the clue that eeprom was available. In our situation a battery would work. If enabled in code, could eeprom be read and written to in the normal convention )(via a command)?
is this what I need? stackoverflow.com/.../how-to-use-backup-sram-as-eeprom-in-stm32f4
Yes, although I think calling it NVRAM will be more inline with what it is.
Guessing ill have to convert this to 205. I had to fix the implicit declarations with prototypes.
static void RCC_AHB1PeriphClockCmd(char, bool); static void RCC_APB1PeriphClockCmd(char, bool); static void PWR_BackupAccessCmd(bool); static void PWR_BackupRegulatorCmd(bool);
but the following are unknown to the 205 RCC_AHB1Periph_BKPSRAM RCC_APB1Periph_PWR
Guessing the 205 has different naming and possibly different address ranges. The data sheet shows AHB1 with a BKPSRAM perf but these are unknown to the IDE. Do I have to enable this in RTE or add an include.
Surely, ST provide examples of how to do this for the specific chip that you have?
Yes, it is important to know (at least for you to know) what ST libraries you are using, assuming that you are in fact using some. There is the STM32F2xx_StdPeriph_Lib of which the example you posted uses. It fully supports the STM32F205. There is also the STM32F2xx_HAL_Driver?