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RTX with External SDRAM LPC1788 - causes bus fault

Hello,

I'm using the Embedded Artists LPC1788 development kit and I'm trying to get a very simple RTX application running using the external SDRAM.

Here is what I have so far:

1) A simple RTX application that runs (blinks an LED) with no problem when I use the internal RAM. This same application crashes with a bus fault in "os_sys_init" when I us the external SDRAM.

2) I configure and initialize the external SDRAM before the call to __main (this is working as I can run the same blinking LED using the SDRAM with no RTX.

3) Even if I let me STACK and HEAP remain in the internal RAM but have variables etc.. in the SDRAM I get the bus fault.

4) The bus fault is an IMPRECISERR: Imprecise data bus error

The call stack looks like this when the fault occurs:

HardFault_Handler -> rt_put_rdy_first() -> rt_dispatch() -> rt_task_create() -> SVC_Hanlder...

Does anyone have any suggestions? I see no reason why this should cause a fault.

Thanks.

MAC

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0 @Marc Crandall over 13 years ago in reply to David Brooks
Hi Dave,

I'm not sure that rounding explains the macro?

Here is my interpretation:

#define tCLK_ns ((double)EMCClock / 1000000000.0 ) // CCLK period in ns #define NS_2_CLKS(ns) ( (uint32_t)( (double)(ns) * tCLK_ns ) + 1 ) // convert ns to CCLKs LPC_EMC->DynamicRP = NS_2_CLKS(18); // tRP: precharge command period (18ns)

Doing the math...

tCLK_ns = 120000000 / 1000000000.0 = 0.12 clk/ns

NS_2_CLKS(18) = (18 * 0.12) + 1 = 3.16 (trunckated = 3)

This means you are setting DynamicRP to 4 clock cycles (since writting a 3 means n+1 clk) and 4 clock cycles is more like 33ns and not the 25ns which 3 clock cycles would be

Do you see my confusion?

Marc
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0 @Marc Crandall over 13 years ago in reply to David Brooks
Hi Dave,

I'm not sure that rounding explains the macro?

Here is my interpretation:

#define tCLK_ns ((double)EMCClock / 1000000000.0 ) // CCLK period in ns #define NS_2_CLKS(ns) ( (uint32_t)( (double)(ns) * tCLK_ns ) + 1 ) // convert ns to CCLKs LPC_EMC->DynamicRP = NS_2_CLKS(18); // tRP: precharge command period (18ns)

Doing the math...

tCLK_ns = 120000000 / 1000000000.0 = 0.12 clk/ns

NS_2_CLKS(18) = (18 * 0.12) + 1 = 3.16 (trunckated = 3)

This means you are setting DynamicRP to 4 clock cycles (since writting a 3 means n+1 clk) and 4 clock cycles is more like 33ns and not the 25ns which 3 clock cycles would be

Do you see my confusion?

Marc
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0 David Brooks over 13 years ago in reply to @Marc Crandall

Yes I do - good observation!

So, I modified the macro to remove the addition of 1...

And here are my new performance results (essentially the same):

Evaluating SDRAM performance: 0
        ...clearing SDRAM (8388608 bytes)...............complete! (185 ms.)
        ...testing SDRAM 16-bit write (4194304 words)...complete! (305 ms.)
        ...testing SDRAM 16-bit read (4194304 words)....complete! (621 ms.), Errors: 0
        ...testing SDRAM 32-bit write (2097152 dwords)..complete! (171 ms.)
        ...testing SDRAM 32-bit read (2097152 dwords)...complete! (298 ms.), Errors: 0

Comprehensive SDRAM performance: 0

...clearing SDRAM (8388608 bytes).....................complete! (185 ms.)
...Walking-bit test: SDRAM 16-bit (4194304 words).....complete! (10.442 sec) (Errors: 0)
...Alternate-bit test: SDRAM 16-bit (4194304 words)...complete! (01.382 sec) (Errors: 0)
...Unique value test: SDRAM 16-bit (4194304 words)....complete! (00.895 sec) (Errors: 0)

...Walking-bit test: SDRAM 32-bit (2097152 dwords)....complete! (09.675 sec) (Errors: 0)
...Alternate-bit test: SDRAM 32-bit (2097152 words)...complete! (00.605 sec) (Errors: 0)
...Unique value test: SDRAM 32-bit (2097152 words)....complete! (00.450 sec) (Errors: 0)