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Vectored IRQ problems in RAM_MODE with LPC2378

Using the MCB2300 board, I am working with the UART1 interrupt mode.
Using a sample program in flash, everything works correctly, but when trying to run the same program at RAM_MODE, I had the following problems:
First LPC2300.S changed so called correctly from RAM Vic Vector Address:

                LDR     PC, IRQ_Addr
;               LDR     PC, [PC, #-0x0120]     ; Vector from VicVectAddr
                LDR     PC, FIQ_Addr

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
                DCD     0                      ; Reserved Address
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler
VIC_Addr        DCD     0xFFFFFF00

Undef_Handler   B       Undef_Handler
SWI_Handler     B       SWI_Handler
PAbt_Handler    B       PAbt_Handler
DAbt_Handler    B       DAbt_Handler
IRQ_Handler     LDR     R5,VIC_Addr
                LDR     PC,[R5]
FIQ_Handler     B       FIQ_Handler


Despite this, and although called correctly IRQ routine, the return is not working properly, to the point of interruption once.
In the program in flash, everything works correctly, but RAM_MODE not load the return address in R14 (LR).

Has anyone had a similar problem or know because this happens?

Parents
  • (I don't know much about this.)

    I guess the below is your IRQ_Handler.

    IRQ_Handler     LDR     R5,VIC_Addr
                    LDR     PC,[R5]
    

    As per
    infocenter.arm.com/.../index.jsp

    2.8.5. Interrupt request

    The Interrupt Request (IRQ) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ, and is masked on entry to an FIQ sequence. As with the nFIQ input, nIRQ passes into the core through a synchronizer.

    Irrespective of whether exception entry is from ARM state or Thumb state, an IRQ handler returns from the interrupt by executing:

    SUBS PC,R14_irq,#4

Reply
  • (I don't know much about this.)

    I guess the below is your IRQ_Handler.

    IRQ_Handler     LDR     R5,VIC_Addr
                    LDR     PC,[R5]
    

    As per
    infocenter.arm.com/.../index.jsp

    2.8.5. Interrupt request

    The Interrupt Request (IRQ) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ, and is masked on entry to an FIQ sequence. As with the nFIQ input, nIRQ passes into the core through a synchronizer.

    Irrespective of whether exception entry is from ARM state or Thumb state, an IRQ handler returns from the interrupt by executing:

    SUBS PC,R14_irq,#4

Children