Hello, I'm implementing I2C Multi-Master/Slave mode handling in the LPC2132 chip. I have few queries about the LPC213x's I2C controller operations.
The user manual says that if the is SI bit (serial interrupt) is cleared or if the I2CSTAT is 0xF8, then there is no activity in the bus.
1. Should the master be polling for this status before initiating a start condition and before every other transaction?
2. Should the software implement an explicit locking mechanism to ensure that the transaction is not interleaved? For instance there could be delays between two bytes (induced by software) in a particular I2C transaction by a master and this should not be interpreted as a 'no serial transaction' by another master. This would allow the other master to snoop the bus while a transaction is already proceeding.
3. If explicit locking must be done in software, how could the controller being in Master mode sense the START/STOP condition driven by other masters?
Thanks in advance.
I don't know your I2C controller, but if you use a hardware implementation, this hardware must support multi master I2C. In this case, the hardware should handle multi master access to the I2C lines. If your hardware does not support multi master, you should think about a software implementation.
Stefan, Thanks for the info. I rechecked the implementation and found that i was missing to handle Arbitration lost in certain parts of the transaction that resulted in the interleaving of data bytes.