why the inter-core SGI interrupt cannot be trigged on GICv3 hardware

Pretty much.

When GICD_CTLR.DS==0, only secure software can access GICR_IGROUPR0 (or GICD_IGROUPRn).  So you would need to program Secure software to program these registers, typically before entering Non-secure state for the first time.

Pretty much.

When GICD_CTLR.DS==0, only secure software can access GICR_IGROUPR0 (or GICD_IGROUPRn).  So you would need to program Secure software to program these registers, typically before entering Non-secure state for the first time.

Got it. Thank you so much.

Hi Martin

I set GICD_CTLR as 0x47 in secure state. I.e, DS is 1.

Now in my 32bit hyp mode, the value of GICR_ISENABLER0 is 0x300, GICR_IGROUPR0 is 0xffff, GICR_IGRPMODR0 is 0. But I still cannot send out a #8 SGI using icc_sgi1r or GICD_SGIR.

The other SPI interrupt, say timer, works fine in the system.

Do you have any other ideas about this issue?

Thanks.

Couple of questions.

Are you doing this write from Secure state?  If so, I would suggest just writing GICR_IGROUPR0 and not setting DS==1.  If not, you can't set the DS bit from Non-secure state.

Also, you don't appear to be setting the ARE bits.  The ARE bits select between the GICv3 and legacy mode.  If you're setting the SRE bits, then the ARE bits should also be set.

EDIT: For reference, attached is a simple assembler program I wrote once to test something.  It's a very minimal GICv3 set up sequence, targeting the Base Platform model.