My hareware environment:
1. a ARMv8 processor , which runs in 64bit EL3 and 32bit EL2&EL1.
2. a GICv3 interrupt controller
Running in 32bit hyp mode, I try to send a SGI interrupt from core0 to core1, but core1 cannot receive this interrupt. Below are what I've tried.
1. I use ICC_SGI1R to send the interrupt. GICD_SGIR cannot be used because "affinity routing" is enabled.
2. Group0, Group1NS and Group1S interrupt are enabled in GICD_CTLR
3. Write GICR_ISENABLER0 to enable SGI interrupt
4. The IRQ/FIQ are unmasked in core1's cpsr5. Group1 intersuprt is enabled in core1's ICC_IGRPEN1 register
But after writting to ICC_SGI1R, I can not find valid bit in pending state register, and core1's ICC_IAR register are also always invalid.
Do you have any suggestions with this issue?
Thanks in advance.
Hi, Can you attach that sample code. I have the same issue.