Hi,
I need to know what happens in the v7 architecture (TI Cortex R4) when both a data abort and FIQ are due to occur.
I found the following document which attempts to address this question but seems to contradict itself:
"The Data Abort has a higher priority than FIQ so that if both occur simultaneously the Data Abort mode is entered first, before immediately processing the FIQ exception. When the FIQ handler returns, it will return to the Data abort vector to handle the data abort."
ARM Information Center
It all makes sense until I read the last sentence which appears to state exactly the opposite of the previous sentence. Can you clear this up for me?
Thanks,
Ryan
Message was edited by: Ryan Smoots Added test information
The device technical reference manual ESM section records:
Group3 errors are reserved for high severity errors generated by diagnostics which have already generated a CPU abort response. Because an abort response in generated, there is no need to generate an interrupt response.
This statement answers my question in a round-about way by stating that the CPU abort response occurs before the FIQ. It appears that the originally posted information from the tech support ARM info center was just misleading.
Hello Ryan,
although I cannot have firm belief, I agree with you.
I interpret "When the FIQ handler returns" as "When the data abort occurs on the FIQ handler return". Isn't it proper?
Best regards,
Yasuhiko Koumoto.
Hi yasuhikokoumoto,
Thank you for your response. I am not sure what you mean by "When the data abort occurs on the FIQ handler return."
Hello,
I mean the stack pop or an interrupt return address might cause the data abort.