HI,currently i am working on project based on stm32f407 chip.my development work has been stopped since two days as i have stuck in hard fault handler. Please guide me how to trace the fault ???i tried every possible way i could.but result in nothing.Pls help me out.thanks in advance
Hi,
the presented code was incomplete. There should be needed a pre-handler which set the hardfault_args of the callee. Although the issue would be almost closed, I show the pre-handler here.
#ifdef CORTEX_M3_M4_M7 void __attribute__ (( naked )) hard_fault_handler(void) { asm volatile( "tst lr, #4\t\n" /* Check EXC_RETURN[2] */ "ite eq\t\n" "mrseq r0, msp\t\n" "mrsne r0, psp\t\n" "b hard_fault_handler_c\t\n" : /* no output */ : /* no input */ : "r0" /* clobber */ ); } #else void __attribute__ (( naked )) hard_fault_handler(void) { asm volatile( "movs r0, #4\t\n" "mov r1, lr\t\n" "tst r0, r1\t\n" /* Check EXC_RETURN[2] */ "beq 1f\t\n" "mrs r0, psp\t\n" "ldr r1,=hard_fault_handler_c\t\n" "bx r1\t\n" "1:mrs r0,msp\t\n" "ldr r1,=hard_fault_handler_c\t\n" : /* no output */ : /* no input */ : "r0" /* clobber */ ); } #endif
In the case of the stack overflow, the handler would be useless. To prevent it, an application program should be run on the PSP, separating with the MSP. However Cortex-M0/M0+ don't support PSP. As for Cortex-M0+, MPU can sometimes be a watchdog for the stack overflow. As for Cortex-M, Uuhm.
Best regards,
Yasuhiko Koumoto.