HI,currently i am working on project based on stm32f407 chip.my development work has been stopped since two days as i have stuck in hard fault handler. Please guide me how to trace the fault ???i tried every possible way i could.but result in nothing.Pls help me out.thanks in advance
Hi kiran1986,
first of all, you should find the cause of the hard fault. To do so, the contents of the stack frame of the hard fault handler would help you. The following is the hard fault handler code from the freescale Kinetis sample codes (sorry I don't have STM environment).
/* Exception frame without floating-point storage * hard fault handler in C, * with stack frame location as input parameter */ void hard_fault_handler_c(unsigned int * hardfault_args) { unsigned int stacked_r0; unsigned int stacked_r1; unsigned int stacked_r2; unsigned int stacked_r3; unsigned int stacked_r12; unsigned int stacked_lr; unsigned int stacked_pc; unsigned int stacked_psr; //Exception stack frame stacked_r0 = ((unsigned long) hardfault_args[0]); stacked_r1 = ((unsigned long) hardfault_args[1]); stacked_r2 = ((unsigned long) hardfault_args[2]); stacked_r3 = ((unsigned long) hardfault_args[3]); stacked_r12 = ((unsigned long) hardfault_args[4]); stacked_lr = ((unsigned long) hardfault_args[5]); stacked_pc = ((unsigned long) hardfault_args[6]); stacked_psr = ((unsigned long) hardfault_args[7]); printf ("[Hard fault handler]\n"); printf ("R0 = %x\n", stacked_r0); printf ("R1 = %x\n", stacked_r1); printf ("R2 = %x\n", stacked_r2); printf ("R3 = %x\n", stacked_r3); printf ("R12 = %x\n", stacked_r12); printf ("LR = %x\n", stacked_lr); printf ("PC = %x\n", stacked_pc); printf ("PSR = %x\n", stacked_psr); #ifndef CW printf ("BFAR = %x\n", (*((volatile unsigned long *)(0xE000ED38)))); printf ("CFSR = %x\n", (*((volatile unsigned long *)(0xE000ED28)))); printf ("HFSR = %x\n", (*((volatile unsigned long *)(0xE000ED2C)))); printf ("DFSR = %x\n", (*((volatile unsigned long *)(0xE000ED30)))); printf ("AFSR = %x\n", (*((volatile unsigned long *)(0xE000ED3C)))); #else printf ("BFAR = %x\n", (*((volatile unsigned int *)(0xE000ED38)))); printf ("CFSR = %x\n", (*((volatile unsigned int *)(0xE000ED28)))); printf ("HFSR = %x\n", (*((volatile unsigned int *)(0xE000ED2C)))); printf ("DFSR = %x\n", (*((volatile unsigned int *)(0xE000ED30)))); printf ("AFSR = %x\n", (*((volatile unsigned int *)(0xE000ED3C)))); #endif for(;;) {} }
Best regards,Yasuhiko Koumoto.
hi ,thanks for prompt reply.by looking at code snippet you sent it gives me status of FSR's and i already have that status. in CFSR IACCVOL bit is set which states somewhat instruction access violation.now my question is my code is written in c how do i troubleshoot which instruction violating access rule when looking into diassembly section.
Hi,
I believe you would like to "get" the actual PC that made the hardfault and not the current PC.
As the stm32f407 is based on Cortex-M4, I believe, you may find the misbehave PC point by looking at the LR register and decide if the PSP or MSP is
the actual stack that is important.
Then open Memory window and and ump MSP or PSP according to LR.
You will find the PC at address (MSP or PSP) + 6 dwords
All of that can be done from the debugger at the hard-fault interrupt breakpoint.
I know a C code is better, but, writing that code is vital only if you plan to "have" lots of hard-faults ... :-)
Hi Kiran,
If you use uVision, see application note 209 from Keil http://www.keil.com/appnotes/files/apnt209.pdf for debugging fault exceptions.
Chapter 12.5 of Joseph Yiu´s book "The definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors, 3rd Edition" explains how to analyze Fault Exceptions.
Cortex-M processors are designed to be programmed entirely in C, but fault exceptions is one of those shadow areas where assembler instructions knowledge is required, at least for debugging.
the presented code was incomplete. There should be needed a pre-handler which set the hardfault_args of the callee. Although the issue would be almost closed, I show the pre-handler here.
#ifdef CORTEX_M3_M4_M7 void __attribute__ (( naked )) hard_fault_handler(void) { asm volatile( "tst lr, #4\t\n" /* Check EXC_RETURN[2] */ "ite eq\t\n" "mrseq r0, msp\t\n" "mrsne r0, psp\t\n" "b hard_fault_handler_c\t\n" : /* no output */ : /* no input */ : "r0" /* clobber */ ); } #else void __attribute__ (( naked )) hard_fault_handler(void) { asm volatile( "movs r0, #4\t\n" "mov r1, lr\t\n" "tst r0, r1\t\n" /* Check EXC_RETURN[2] */ "beq 1f\t\n" "mrs r0, psp\t\n" "ldr r1,=hard_fault_handler_c\t\n" "bx r1\t\n" "1:mrs r0,msp\t\n" "ldr r1,=hard_fault_handler_c\t\n" : /* no output */ : /* no input */ : "r0" /* clobber */ ); } #endif
In the case of the stack overflow, the handler would be useless. To prevent it, an application program should be run on the PSP, separating with the MSP. However Cortex-M0/M0+ don't support PSP. As for Cortex-M0+, MPU can sometimes be a watchdog for the stack overflow. As for Cortex-M, Uuhm.
Best regards,
Yasuhiko Koumoto.