For example, the codes are executed in core0.
codes:
(1) send SGI to core1 ICC_SGI1R_EL1
(2) set(a) = 1
i) Then the core1 will first see the irq or the change of variable a?
ii) If I add ISB between (1) and (2), what happended?
iii) If I add DMB (read and write)between (1) and (2), what happended?
iv) If I add DSB (read and write)between (1) and (2), what happended?
After I tested, it seems that only iv) which add DSB makes core1 see (2) after (1).
I had checked the discription of DSB, I don't think any rules match this.
Any help will be appreciated. Thanks!
You are right. It should both add memory barrier, to make the memory accesses in order.
As to make other cores see SGI as soon as possible, I decided to add ISB;DSB.
Becasue, the GICv3 document said:
Architectural execution of a DSB instruction guarantees that:
"The last value written to ICC_SGI0R_EL1 or ICC_SGI1R_EL1 is observed by the associated Redistributor.
An ISB or other context synchronization operation must precede the DSB to ensure visibility of System register writes."
And it seems that it has no relationship with order, just to make the write arrive the Redistributor as fast as possible.