For example, the codes are executed in core0.
codes:
(1) send SGI to core1 ICC_SGI1R_EL1
(2) set(a) = 1
i) Then the core1 will first see the irq or the change of variable a?
ii) If I add ISB between (1) and (2), what happended?
iii) If I add DMB (read and write)between (1) and (2), what happended?
iv) If I add DSB (read and write)between (1) and (2), what happended?
After I tested, it seems that only iv) which add DSB makes core1 see (2) after (1).
I had checked the discription of DSB, I don't think any rules match this.
Any help will be appreciated. Thanks!
Thomas,
ISB between (1) and (2) assures that the code is executed in order. But does not mean the write to the memory appears in order.The DMB/DSB assures that any write _before_ the DMB did reach the register/memory (or cache). But DMB w/o the ISB could mean, that the (2) is done before (1).But even if you add ISB; DMB you cannot be sure that core 1 sees a == 1 or its previous value as you only know the order of action in the one core, but not how this is distributed between the cores.So actually, you should reverse the order of (1) and (2).
You are right. It should both add memory barrier, to make the memory accesses in order.
As to make other cores see SGI as soon as possible, I decided to add ISB;DSB.
Becasue, the GICv3 document said:
Architectural execution of a DSB instruction guarantees that:
"The last value written to ICC_SGI0R_EL1 or ICC_SGI1R_EL1 is observed by the associated Redistributor.
An ISB or other context synchronization operation must precede the DSB to ensure visibility of System register writes."
And it seems that it has no relationship with order, just to make the write arrive the Redistributor as fast as possible.
I am such uncertain about what I said after I rethink this several times.
"Architectural execution of a DSB instruction guarantees that:
The last value written to ICC_SGI0R_EL1 or ICC_SGI1R_EL1 is observed by the associated Redistributor."
This sentense means DSB will wait until the "ICC_SGI1R_EL1 is observed by the associated Redistributor".
Is this necesary in SMP? I think maybe not. One core doesn't need to wait this to be happen before it does next thing.
Do you agree?
I am such confused on this kind of issue!!!
Well, yes. It is kinda confusing. I was thinking myself if there is a situation where this is needed. But I did not find a scenario.So, one core writes ICC_SGI0R_EL1, the write will be delayed due to some pipeline, store-buffering effect. Now this core does something which a) either disturbs the previous write or b) depends on this write going through.For (a), I cannot find something.
For (b), neither .. :(