Hello to all AHB experts,
I have some question about AHB-Lite interconnection.
If I want to build 2 masters share 1 slave systems. I add a arbiter in the interconnect circuit, so that only one master could access the slave at a time.
My question is how the slave response mux to the masters?
1. If (HTRANS1==NONSEQ) for master1, (HTRANS2==NONSEQ) for master2, only a master will see the HREADY response at data phase whose grant by the arbiter?
2. If (HTRANS1==ILDE ) for master1, (HTRANS2==IDLE ) for master2, two masters will see the HREADY response at data phase at a time?
3. If (HTRANS1==NONSEQ) for master1, (HTRANS2==IDLE ) for master2, two masters will see the HREADY response at data phase at a time?
Thanks a lot.
Q1) Depends on the BusMatrix design.
The mandatory HREADY=1 HRESP=OKAY data phase response to an IDLE address phase must be given as soon as the data phase starts, so if the BusMatrix could not route this IDLE transfer through to a slave and get an immediate response from that slave, the BusMatrix logic facing the master would give this response. Something needs to return the mandatory response, and I would expect it to be the BusMatrix in most cases.
Q2) Again I think this depends on the BusMatrix or interconnect arbitration logic, when it decides to switch between requesting masters.
However if this arbitration logic does switch to a new master source part way through another master's access sequence, the arbitration logic then needs to modify the original master transfer characteristics to be legal for when that master is next selected. So the original master's "broken" sequence must restart with a NONSEQ access, and HBURST would need modifying if it had originally signalled a defined length burst.
The original master isn't aware that it didn't complete its sequence in one single sequence, all it saw was wait states while the other master was accessing the slave, so the arbiter that did the sequence breaking has to ensure the transfers the slave sees are legal (again the starting with a NONSEQ and HBURST being correct for the transfers remaining to be performed by this "new" sequence").
Q3) Don't see any issues with what you have described.
Just make sure that your burst tracking logic is aware that the HTRANS sequence could include BUSY transfers between the NONSEQ and final SEQ transfer of the INCR4 burst.
Thanks for your clear description.