CTRLSTAT = 0xffffffff

Thanks for Reply sir,

                              in above post you wrote "0x40023c04=0x45670123. 0x4002c304=0xcdef89ab" hear both addresses are different , in stm32f4 reference manual  3.6.1 he mentioned that both keys 0x45670123 and 0xcdef89ab should be send to FLASH_KEYR(0x40023C04) register please make a clarity on that and another thing is my flash Unlock was unsuccess full.

my procedure was

halt

reset

reading status of FLASH_CR register if LOCK bit is set then

sending 0x45670123 and 0xcdef89ab  to FLASH_KEYR register.

delay: for loop ->1000

then reading status of FLASH_CR register.

Thanks and Regards.

Thanks for Reply sir,

                              in above post you wrote "0x40023c04=0x45670123. 0x4002c304=0xcdef89ab" hear both addresses are different , in stm32f4 reference manual  3.6.1 he mentioned that both keys 0x45670123 and 0xcdef89ab should be send to FLASH_KEYR(0x40023C04) register please make a clarity on that and another thing is my flash Unlock was unsuccess full.

my procedure was

halt

reset

reading status of FLASH_CR register if LOCK bit is set then

sending 0x45670123 and 0xcdef89ab  to FLASH_KEYR register.

delay: for loop ->1000

then reading status of FLASH_CR register.

Thanks and Regards.

I'm sorry, 0x4002c304 was a typo, I believe the right address should be 0x40023c04.

Did you try reading FLASH_SR right after writing the two values to FLASH_KEYR ?

What are the values you read from FLASH_SR and FLASH_CR ?

thank you for suggestion,

after sending the key to FLASH_KEYR register

reading

FLASH_CR = 0x80000000

FLASH_SR = 0x000000c0

Thanks & regards.

Hmm, at least you can read the registers.

I'm about to run out of ideas, but maybe it will help, if you try inserting dummy-clocks (for instance 50 zero-bits) between writing the unlocking-sequence, like this:

Write the first word, send 50 dummy-clocks, write the second word, send 50 dummy-clocks, read CR, read CR.

thanks for quick reply,

i got error resolved, the problem is each time while writing i selcting CSW register, with out that i wrote the following sequence

setting CSW register with proper bit settings then

TAR = FLASH_KEYR

DRW = KEY1

idle cycle

TAR = FLASH_KEYR

DRW = KEY2

idle cycle

now i am reading

FLASH_CR = 0x00000000

FLASH_SR = 0x000000C0

after above

i wrote data to flash memory as following procedure

checking BSY bit in FLASH_SR register wait until this bit is cleared.

setting PG bit and 32bit selection by

FLASH_CR = 0x00000201

after that I am trying to read the FLASH_CR and FLASH_SR register

but i got as following

FLASH_CR = 0x00000000

FLASH_SR = 0x000000C0

data is not updated on FLASH_CR register???

my doubt is after halt and reset no registers are modified why??

Try writing 0x00000200 first, then 0x00000201.

For instance:

read 0x40023c0c  (FLASH_SR)

read 0x40023c10 (FLASH_CR)

0x40023c10 = 0x00000200;

read 0x40023c0c  (FLASH_SR)

read 0x40023c10 (FLASH_CR)

0x40023c10 = 0x00000201;

read 0x40023c0c  (FLASH_SR)

read 0x40023c10 (FLASH_CR)

-But before that, I think it would be a good idea to read FLASH_OPTCR (0x40023c14) and check that it allows you to write to the Flash-memory.

This could also be a power issue. Make sure VOS in PWR_CR is set to Scale1 mode. (there's also a VOS_RDY bit you'll have to wait for)

thank you sir,

                    i tried your above approach i got FLASH_OPTCR = 0x0FFFAAED , and PWR_CR = 0x0000C000. is there any wrong with these values??

Thanks & Regards,

FLASH_OPTCR looks good to me; excellent!

I think your PWR_CR looks good too. Mine is also 0x0000c000.

I think I'll have to call for jyiu's help now, because I've run out of clues what can be wrong.

Although we're dealing with a problem specific to the STM32F407 at the moment, I just came across this document from ARM about the Debug Interface Architecture: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0031a/index.html

-You can download it for free; you just need to register first.

err....sorry.... I don't think I can help in this STM32F4 specific question.

My suggestion is to post this on STM32 forum and see if anyone there can help.

regards,

Joseph

Well, it was worth the try, thank you for taking the time to look at it, Joseph.

harshan_behra -This is a very special case, only very few people have been working with it, so there might not be many people who can answer.

That means you're in pioneer-land, which is one of the most interesting places to be, but also one of the most difficult places to be at the same time.

If / when you find the answer, please let us know what caused the problem.

I just looked in the sources for the stlink tool. This might bring you to the solution.

In the file "stlink-common.c", line 1593 ...

After the sequence you mentioned, it writes a small piece of code into the SRAM and executes it.

This piece of code copies a data block from the address that register r0 points to, to the address that register r1 points to, the length of the data block is r2 bytes.

So this small piece of code can be used for both reading flash memory and writing flash memory.

In the same file, line 1765, you'll find the routine (run_flash_loader) that sets the parameters and runs the piece of code in SRAM.

The routine, which sets the value of a core register is also interesting, it's called stlink_write_reg, and is actually located in stlink-usb.c as _stlink_usb_write_reg at line 680.

Thank you sir,

                      I found the bug and fixed it, the bug was i have to check each time whether BSY bit in FLASH_SR was set or not that makes the consistency. Thank you for your valuable suggestions and support

Thanks & Regards,

harshan

Excellent news. Thank you for letting us know and also that you kept going when it wasn't easy.

I am very convinced that this will be valuable help for anyone who implements the SWD protocol in their own applications.

hi sir,

          may i know where could i found detailed explanation about watch points and break points ?? in reference manual he given a little bit but i need in programmer view where could i get such information??

Thanks & Regards.

Unfortunately I'm not an expert in this area, so I don't know much about breakpoints and watchpoints.

I went to the ARM Information Center and searched for 'watchpoint', as this is not technology specific to the STM device, but it's ARM technology.

Scrolling down, I find the results for ARM Cortex-M4 Processor Technical Reference Manual, I click it, and I click the DWT Programmers Model link in there.

This shows addresses of hardware registers.

If you look at CWT_CTRL, it says "See [a]", which refers to a note giving you some more information: There are (up to) four comparators for watchpoints and triggers.

In RM0090, sectino 38.13, you'll find some information about what's implemented in your device, combining this with the information found in the Cortex-M4 Technical Reference Manual should get you a bit further.

Please try ARMv7-M Architecture Reference Manual. You need to register on ARM web site to download this document.

(ARMv7-M Architecture Reference Manual)

Section C 1.8 for DWT (watchpoint), C 1.11 for FPB (breakpoint) and C 1.6 for debug registers in the processor for halting control.

regards,

Joseph