CTRLSTAT = 0xffffffff

I just looked in the sources for the stlink tool. This might bring you to the solution.

In the file "stlink-common.c", line 1593 ...

After the sequence you mentioned, it writes a small piece of code into the SRAM and executes it.

This piece of code copies a data block from the address that register r0 points to, to the address that register r1 points to, the length of the data block is r2 bytes.

So this small piece of code can be used for both reading flash memory and writing flash memory.

In the same file, line 1765, you'll find the routine (run_flash_loader) that sets the parameters and runs the piece of code in SRAM.

The routine, which sets the value of a core register is also interesting, it's called stlink_write_reg, and is actually located in stlink-usb.c as _stlink_usb_write_reg at line 680.

I just looked in the sources for the stlink tool. This might bring you to the solution.

In the file "stlink-common.c", line 1593 ...

After the sequence you mentioned, it writes a small piece of code into the SRAM and executes it.

This piece of code copies a data block from the address that register r0 points to, to the address that register r1 points to, the length of the data block is r2 bytes.

So this small piece of code can be used for both reading flash memory and writing flash memory.

In the same file, line 1765, you'll find the routine (run_flash_loader) that sets the parameters and runs the piece of code in SRAM.

The routine, which sets the value of a core register is also interesting, it's called stlink_write_reg, and is actually located in stlink-usb.c as _stlink_usb_write_reg at line 680.

Thank you sir,

                      I found the bug and fixed it, the bug was i have to check each time whether BSY bit in FLASH_SR was set or not that makes the consistency. Thank you for your valuable suggestions and support

Thanks & Regards,

harshan

Excellent news. Thank you for letting us know and also that you kept going when it wasn't easy.

I am very convinced that this will be valuable help for anyone who implements the SWD protocol in their own applications.

hi sir,

          may i know where could i found detailed explanation about watch points and break points ?? in reference manual he given a little bit but i need in programmer view where could i get such information??

Thanks & Regards.

Unfortunately I'm not an expert in this area, so I don't know much about breakpoints and watchpoints.

I went to the ARM Information Center and searched for 'watchpoint', as this is not technology specific to the STM device, but it's ARM technology.

Scrolling down, I find the results for ARM Cortex-M4 Processor Technical Reference Manual, I click it, and I click the DWT Programmers Model link in there.

This shows addresses of hardware registers.

If you look at CWT_CTRL, it says "See [a]", which refers to a note giving you some more information: There are (up to) four comparators for watchpoints and triggers.

In RM0090, sectino 38.13, you'll find some information about what's implemented in your device, combining this with the information found in the Cortex-M4 Technical Reference Manual should get you a bit further.

Please try ARMv7-M Architecture Reference Manual. You need to register on ARM web site to download this document.

(ARMv7-M Architecture Reference Manual)

Section C 1.8 for DWT (watchpoint), C 1.11 for FPB (breakpoint) and C 1.6 for debug registers in the processor for halting control.

regards,

Joseph