Hi,
I want to evaluate different cache settings such as block size, way size, replacement policy, prefetch distance, and prefetch block numbers etc for all cache levels so that I can determine the best settings for a specific set of applications. Is it possible to do this in Carbon SOC designer?
I have read pl310 cache controller technical reference and known that for L2 cache I can adjust the AUX and Prefetch control registers, to affect some configurations for prefetch offset etc on real hardware and on Carbon SOC designer. However, I would like to explore a greater range of settings than seem to be available in the pl310 controller technical reference, as such I would like to know if it is possible to explore cache performance for those additional settings using Carbon SOC designer.
If this is not possible would you know of a cache simulator which may satisfy this purpose?
Thanks in advance!
Ting
Hi Ting,
Yes, SoC Designer can be used for this purpose. ARM Cycle Models are available for a number of ARM CPUs as well as the PL310 L2 cache controller. There are also example systems available which include the PL310. You can review these at http://www.armsystemexchange.com
An article which will give you a good idea of what can be done is also available: https://community.arm.com/processors/b/blog/posts/using-arm-cycle-models-to-understand-the-cortex-r8 This article covers the type of analysis you are asking about for the Cortex-R8 and PL310
Please don't hesitate to ask if you have any questions or want to get started with SoC Designer.
Jason
Thanks very much Jason! I have read those pages carefully. Great help.