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Issue virtual timer interrupt

armdev

Hi,

I am facing an issue where I am setting virtual timer to fire at particular interval (Juno PPI4 , interrupt no 27) from EL1NS mode and

when the timer interrupt happens the control is falling to EL2t IRQ handler rather than guest aarch64 IRQ handler. I confirm that I am setting EL1 to aarch64 state into HCR_EL2 register (RW = 1).

I see below register values -

PC = 0x80214480

VBAR_EL2 = 0x80214400

ESR_EL2 = 0x356ABA3B { EC = 13, IL = 16 bit instruction trapped, ISS = 23771707 }

                 

Does any one knows how to resolve this ?  I am not sure if i am missing anything ?

Thanks,

Parents
  • +1

    Despite the name, the Virtual Timer will be generating a physical interrupt.  I'm guessing you've got it configured as Group 1 in the GIC, which means it will be sent as an IRQ exception.  If your taking the exception to EL2, then you'll have HCR_EL2.IMO==1 (route physical IRQs to EL2, unless already routed to EL3).

    If you want the IRQ taken to NS.EL1 you have a couple of choices:

    * HCR_EL2.IMO==0:  this will route physical IRQs to EL1 instead of EL2.  This might not be what you want if you only need certain IRQs in EL1 and others in EL2.

    * Add EL2 code to forward the interrupt to NS.EL1 as a virtual IRQ, using the GIC's list registers.

    NOTE: The ESR_ELx registers aren't used for IRQs or FIQs.

Reply
  • +1

    Despite the name, the Virtual Timer will be generating a physical interrupt.  I'm guessing you've got it configured as Group 1 in the GIC, which means it will be sent as an IRQ exception.  If your taking the exception to EL2, then you'll have HCR_EL2.IMO==1 (route physical IRQs to EL2, unless already routed to EL3).

    If you want the IRQ taken to NS.EL1 you have a couple of choices:

    * HCR_EL2.IMO==0:  this will route physical IRQs to EL1 instead of EL2.  This might not be what you want if you only need certain IRQs in EL1 and others in EL2.

    * Add EL2 code to forward the interrupt to NS.EL1 as a virtual IRQ, using the GIC's list registers.

    NOTE: The ESR_ELx registers aren't used for IRQs or FIQs.

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