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Issue virtual timer interrupt

armdev

Hi,

I am facing an issue where I am setting virtual timer to fire at particular interval (Juno PPI4 , interrupt no 27) from EL1NS mode and

when the timer interrupt happens the control is falling to EL2t IRQ handler rather than guest aarch64 IRQ handler. I confirm that I am setting EL1 to aarch64 state into HCR_EL2 register (RW = 1).

I see below register values -

PC = 0x80214480

VBAR_EL2 = 0x80214400

ESR_EL2 = 0x356ABA3B { EC = 13, IL = 16 bit instruction trapped, ISS = 23771707 }

                 

Does any one knows how to resolve this ?  I am not sure if i am missing anything ?

Thanks,

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  • 0 Arm Employee Badge in reply to armdev

    If you put a breakpoint on both IRQ vector entries.  When you hit on the 0x80 entry, what do SPSR_EL2 and ELR_EL2 report?

    "1) Why it is 0x80 if I am selecting SPSel = 1 and my Mode.M = 9 when I break through DS-5 ?"

    Where/when are you selecting Mode.M=0x9?  Not sure I follow - but 0x9 is the value for EL2 not EL1.

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  • 0 Arm Employee Badge in reply to armdev

    If you put a breakpoint on both IRQ vector entries.  When you hit on the 0x80 entry, what do SPSR_EL2 and ELR_EL2 report?

    "1) Why it is 0x80 if I am selecting SPSel = 1 and my Mode.M = 9 when I break through DS-5 ?"

    Where/when are you selecting Mode.M=0x9?  Not sure I follow - but 0x9 is the value for EL2 not EL1.

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