I am working on smp_prime code of ARM - A9. And a i want to use that code for cortex A7.
But after making changes like setting smp bit in ACTLR, Making the memory region device and non coherent- then if i enable the MMU bit from system control register. ARM cortex A7 crashes.
Please give me answer of following questions.
1) Is there any huge bit manipulation required to use same code of A9 for A7 ?
2) What is correct way of enabling MMU ?
See jason what i did is :
case 1:::
1) I have set TEX=1,C=1,B=1 in TTB section frame.: This is for write allocate and write back
2) I have keep all functions same as A9 just i changed this flags and memory areas with i want as device and shared.
3) Then i enabled MMU along with Branch prediction and Instruction cache.
4) then jump to main.
5) And then from main if i enable data cache arm crashes.
6) And also if enable Data cache i got junk characters on screen.
case :::
1) if i set TEX as 0, C=1, B=0 then all programs works fine.
Problem is it is write through and i don't want this.
I want my code for 0x80000000 should be cacheble and remaining normal.
Tell me how can i get this