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A53 Core做FPGA原型验证时，其中的clock gating模块如何处理？

foolsun

A53 Core做FPGA原型验证时，其中的clock gating模块如何处理？

是改成FPGA的clock gating模块吗？那FPGA上也没那么多的Cell可以用！

还是靠综合工具自动处理？

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