cortex M0 ip simulition err

LIBRARY ieee;                                               

USE ieee.std_logic_1164.all;                                

 ENTITY AHBLITE_SYS_vhd_tst IS

constant CLKPeriod: time := 10 ns;

END AHBLITE_SYS_vhd_tst;

 ARCHITECTURE AHBLITE_SYS_arch OF AHBLITE_SYS_vhd_tst IS                                               

SIGNAL CLK : STD_LOGIC:='0';

SIGNAL LED : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL RESET : STD_LOGIC:='0';

COMPONENT AHBLITE_SYS

PORT (

CLK : IN STD_LOGIC;

LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

RESET : IN STD_LOGIC );

END COMPONENT;

BEGIN

i1 : AHBLITE_SYS PORT MAP ( CLK => CLK, LED => LED, RESET => RESET );

simProcess: process

    begin

        RESET <= '0';   wait for 40 ns;

        RESET <= '1' ;  wait for 1000 ns;

        RESET <= '1' ;  wait;

    end process simprocess;

 ClockProcess: process(CLK, RESET)

    begin

        if (RESET = '0') then          CLK <= '0';

        else       CLK <= not CLK after CLKPeriod;

        end if;

    end process ClockProcess;                                      

END AHBLITE_SYS_arch;