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Using ARM cycle model studio compile RTL code, could not generate .clock file.

I used Cycle Model Studio to compile the RTL code to SystemC code, and found that in "Generated files", the .clock and .cycle files are empty?  what 's the possible reason that caused this issue?

PS: the RTL code is temporal logical and CMS version is 9.4.0

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  • Thanks for asking about Cycle Model Studio.

    The .clock and .cycle files are for information only. They don't impact the functionality of the generated model and it's not automatically an error if the files are empty.

    The .clock file reports clocks found in the design and the .cycle file reports cyclic logic in the design.

    Always check for alerts in the log files and don't hesitate to ask if you have more questions about CMS.

    Thanks,

    Jason

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  • Thanks for asking about Cycle Model Studio.

    The .clock and .cycle files are for information only. They don't impact the functionality of the generated model and it's not automatically an error if the files are empty.

    The .clock file reports clocks found in the design and the .cycle file reports cyclic logic in the design.

    Always check for alerts in the log files and don't hesitate to ask if you have more questions about CMS.

    Thanks,

    Jason

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