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Nested Interrupt CM3

Nino Caruso
Note: This was originally posted on 29th May 2012 at http://forums.arm.com

Hello everyone,
i just want to know how does nesting interrupt work on Cortex M3.
Register PRIMASK, BASEPRI and FAULTMASK are usefull if i want to ignore ,when occurs, certain interrupt (by setting a priority level threshold) ignore= interrup not accepted,  interrupt not nested
Register like SETENA enable or disable specific interrupt ( by # )
When the processor  is handling an exception and comes an interrupt that has upper priority level, the current exception is nested (save register etc etc ) and the new exception is executed. If the priority of the new interrupt is lower , the NVIC will not nest the interrupt, it will be ignored.

is correct what i've understood? is there something that i miss?



thank you in advance
Nino

ps i'm sorry for my bad english
  • Note: This was originally posted on 4th June 2012 at http://forums.arm.com

    -"In such case, the pending status of this interrupt will be set"
    in  particular : where the pendig status is set, for an internal interrupt  if the SETPEND is only for external interrupt?
    similarly for register SETENA/CLRENA, how can i enable/disable internal interrupt if the registers(SETENA,CLRENA) are associated only to  external interrupt?


    -How can the CM3 determine the priority of an internal interrupt that is programmable if there is not a priority level register associated to it?
    (ex: BUS FAULT exception #4 has a priority level programmable, where cm3 find it?)


    thank you in advance
  • Note: This was originally posted on 6th June 2012 at http://forums.arm.com

    why there are 2 registers (SETENA and CLRENA) when i can enable/disable external interrupt by using one?  (bit =1 external interrupt enabled , bit= 0 ext. int. disabled)
    i know that writing 1 in reg CLRENA means that clear to 0 the respectively bit in the SETENA reg, but with one reg it works better

    another question , how nvic schedule the pending interrupt (external or internal ) by priority?


    thank you
  • Note: This was originally posted on 11th June 2012 at http://forums.arm.com

    WFI wakeup behavior :
    when an interrupt arrives it's priority must be higher than "current privilege level",BASEPRI and the mask registers, than it wakeup the processor that execute the handler. Else if the interrupt will not be accepted due the priority it will not wake up the processor, in this case it will be set as pending? is there a possibility that the interrupt wakeup the processor but will be set as pending?

    Similar questions for WFE wakeup behavior, is there a possibility that a event wakeup the processor but it will be set as pending? if yes,where is it set?  in the register SETPEND?

    thank you
  • Note: This was originally posted on 12th June 2012 at http://forums.arm.com

    Questions about WICSENSE,WICLOAD,WICMASK.

    both WICMASK and WICSENSE are used to indicate that the WIC must wake up in response to the corresponding WICINT signal, but in particular WICSENSE what does it do?

    WICMASK comes from the core of CM3(from NVIC) to WIC but what make me confuse is that WICSENSE comes out from the WIC to i don't know where.

    How can WICLOAD is usefull(togheter WICMASK) to enable certain interrupt or event to cause a wakeup?

    WIC works only when there is deep sleep, normal sleep don't causes power down to the nvic like deep sleep, right?

    Thank you in advance
  • Note: This was originally posted on 5th June 2012 at http://forums.arm.com

    The pending status for internal exceptions are set in System Handler Control and State Register.
    The priority of internal exceptions can be configured in System Handler Priority Register1, 2,3
    Please go through the CM3 System Handler Priority Register1, 2, 3 and System Handler Priority Regsiter descriptions for the usage

    Thanks and Regards,
    Prasant

  • Arm Employee Badge
    Note: This was originally posted on 30th May 2012 at http://forums.arm.com

    Hi Nino,

    The use of "ignore" is possibly not the best word.
    If an interrupt occurred, but:
    - the PRIMASK or FAULTMASK or BASEPRI is set, which result in blocking the interrupt, or
    - the Cortex-M3 is already running another interrupt handler with higher or same priority
    The processor will not accept the new interrupt.
    In such case, the pending status of this interrupt will be set, and the processor will process it later if:
    - the PRIMASK / FAULTMASK / BASEPRI is cleared, or
    - the processor finished the current executing Interrupt Service Routine (ISR) and exited the handler, which result in current priority level change.

    In overall, the interrupt request is not lost, but could be delayed by the interrupt masking registers or other interrupt services.

    regards,
    Joseph
  • Arm Employee Badge
    Note: This was originally posted on 11th June 2012 at http://forums.arm.com

    Regarding WFI:

    >else if the interrupt will not be accepted due the priority it will not  wake up the processor, in this case it will be set as pending?

    Yes, correct.

    >is there a possibility that the interrupt wakeup the processor but will be set as pending?

    Yes, by setting PRIMASK.

    Regarding WFE:
    > Similar questions for WFE wakeup behavior, is there a possibility that a  event wakeup the processor but it will be set as pending?

    Yes, using the SEVONPEND feature. By setting bit 4 of System Control Register, an event is generate for a new pending of a interrupt, which can wake up the processor from WFE sleep.

    >  if yes,where is it set?  in the register SETPEND?

    Yes, in the pending status register. You can read back the current pending status from SETPEND (NVIC->ISPR) as well as CLRPEND (NVIC->ICPR).

    regards,
    Joseph
  • Arm Employee Badge
    Note: This was originally posted on 12th June 2012 at http://forums.arm.com

    Hi Nino,

    I guess you are working for a company which is a ARM customer? If yes, for these RTL related question please use ARM support. (Please use your work email address so that the support team can identify you). It is inconvenient to answer this kind of questions on a public forum as some information could be confidential. Thanks.
    regards,
    Joseph
  • Arm Employee Badge
    Note: This was originally posted on 8th June 2012 at http://forums.arm.com

    Hi,

    It is intentional to use two addresses to set and clear the NVIC enable register.
    If it use just one address for normal read and write, you need to use a read-modify-write operation to change a bit in this register. During this sequence, if a interrupt happen and the interrupt handler changed another bit in the register, when you resume the read-modify-write, you will overwrite the changes made by the interrupt handler.

    The same issue can happen in system with RTOS, where context swtiching can happen in the middle of the read-modify-write, and after the task is resumed it could overwrite the changes made by another task.

    By using two register addresses, you only need to have one write to enable/disable a interrupt, without the need to read back the status of the whole register beforehand.

    The NVIC has a number of priority level registers for each interrupts. It compare the priority levels of pending interrupt requests against each other, as well as to the current level of the processor. This is done in hardware. If the priority level of a pending interrupt is higher than others (including the current level of the processor), it will signal to the processor core and the processor will suspend current task and start processing the interrupt request as soon as possible.

    regards,
    Joseph