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Nested Interrupt CM3

Nino Caruso
Note: This was originally posted on 29th May 2012 at http://forums.arm.com

Hello everyone,
i just want to know how does nesting interrupt work on Cortex M3.
Register PRIMASK, BASEPRI and FAULTMASK are usefull if i want to ignore ,when occurs, certain interrupt (by setting a priority level threshold) ignore= interrup not accepted,  interrupt not nested
Register like SETENA enable or disable specific interrupt ( by # )
When the processor  is handling an exception and comes an interrupt that has upper priority level, the current exception is nested (save register etc etc ) and the new exception is executed. If the priority of the new interrupt is lower , the NVIC will not nest the interrupt, it will be ignored.

is correct what i've understood? is there something that i miss?



thank you in advance
Nino

ps i'm sorry for my bad english
Parents
  • Note: This was originally posted on 11th June 2012 at http://forums.arm.com

    WFI wakeup behavior :
    when an interrupt arrives it's priority must be higher than "current privilege level",BASEPRI and the mask registers, than it wakeup the processor that execute the handler. Else if the interrupt will not be accepted due the priority it will not wake up the processor, in this case it will be set as pending? is there a possibility that the interrupt wakeup the processor but will be set as pending?

    Similar questions for WFE wakeup behavior, is there a possibility that a event wakeup the processor but it will be set as pending? if yes,where is it set?  in the register SETPEND?

    thank you
Reply
  • Note: This was originally posted on 11th June 2012 at http://forums.arm.com

    WFI wakeup behavior :
    when an interrupt arrives it's priority must be higher than "current privilege level",BASEPRI and the mask registers, than it wakeup the processor that execute the handler. Else if the interrupt will not be accepted due the priority it will not wake up the processor, in this case it will be set as pending? is there a possibility that the interrupt wakeup the processor but will be set as pending?

    Similar questions for WFE wakeup behavior, is there a possibility that a event wakeup the processor but it will be set as pending? if yes,where is it set?  in the register SETPEND?

    thank you
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