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Nested Interrupt CM3

Nino Caruso
Note: This was originally posted on 29th May 2012 at http://forums.arm.com

Hello everyone,
i just want to know how does nesting interrupt work on Cortex M3.
Register PRIMASK, BASEPRI and FAULTMASK are usefull if i want to ignore ,when occurs, certain interrupt (by setting a priority level threshold) ignore= interrup not accepted,  interrupt not nested
Register like SETENA enable or disable specific interrupt ( by # )
When the processor  is handling an exception and comes an interrupt that has upper priority level, the current exception is nested (save register etc etc ) and the new exception is executed. If the priority of the new interrupt is lower , the NVIC will not nest the interrupt, it will be ignored.

is correct what i've understood? is there something that i miss?



thank you in advance
Nino

ps i'm sorry for my bad english
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  • Arm Employee Badge
    Note: This was originally posted on 12th June 2012 at http://forums.arm.com

    Hi Nino,

    I guess you are working for a company which is a ARM customer? If yes, for these RTL related question please use ARM support. (Please use your work email address so that the support team can identify you). It is inconvenient to answer this kind of questions on a public forum as some information could be confidential. Thanks.
    regards,
    Joseph
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  • Arm Employee Badge
    Note: This was originally posted on 12th June 2012 at http://forums.arm.com

    Hi Nino,

    I guess you are working for a company which is a ARM customer? If yes, for these RTL related question please use ARM support. (Please use your work email address so that the support team can identify you). It is inconvenient to answer this kind of questions on a public forum as some information could be confidential. Thanks.
    regards,
    Joseph
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