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Nested Interrupt CM3

Note: This was originally posted on 29th May 2012 at http://forums.arm.com

Hello everyone,
i just want to know how does nesting interrupt work on Cortex M3.
Register PRIMASK, BASEPRI and FAULTMASK are usefull if i want to ignore ,when occurs, certain interrupt (by setting a priority level threshold) ignore= interrup not accepted, interrupt not nested
Register like SETENA enable or disable specific interrupt ( by # )
When the processor is handling an exception and comes an interrupt that has upper priority level, the current exception is nested (save register etc etc ) and the new exception is executed. If the priority of the new interrupt is lower , the NVIC will not nest the interrupt, it will be ignored.

is correct what i've understood? is there something that i miss?

thank you in advance
Nino

ps i'm sorry for my bad english

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Joseph Yiu over 12 years ago

Note: This was originally posted on 8th June 2012 at http://forums.arm.com

Hi,

It is intentional to use two addresses to set and clear the NVIC enable register.
If it use just one address for normal read and write, you need to use a read-modify-write operation to change a bit in this register. During this sequence, if a interrupt happen and the interrupt handler changed another bit in the register, when you resume the read-modify-write, you will overwrite the changes made by the interrupt handler.

The same issue can happen in system with RTOS, where context swtiching can happen in the middle of the read-modify-write, and after the task is resumed it could overwrite the changes made by another task.

By using two register addresses, you only need to have one write to enable/disable a interrupt, without the need to read back the status of the whole register beforehand.

The NVIC has a number of priority level registers for each interrupts. It compare the priority levels of pending interrupt requests against each other, as well as to the current level of the processor. This is done in hardware. If the priority level of a pending interrupt is higher than others (including the current level of the processor), it will signal to the processor core and the processor will suspend current task and start processing the interrupt request as soon as possible.

regards,
Joseph
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Joseph Yiu over 12 years ago

Note: This was originally posted on 8th June 2012 at http://forums.arm.com

Hi,

It is intentional to use two addresses to set and clear the NVIC enable register.
If it use just one address for normal read and write, you need to use a read-modify-write operation to change a bit in this register. During this sequence, if a interrupt happen and the interrupt handler changed another bit in the register, when you resume the read-modify-write, you will overwrite the changes made by the interrupt handler.

The same issue can happen in system with RTOS, where context swtiching can happen in the middle of the read-modify-write, and after the task is resumed it could overwrite the changes made by another task.

By using two register addresses, you only need to have one write to enable/disable a interrupt, without the need to read back the status of the whole register beforehand.

The NVIC has a number of priority level registers for each interrupts. It compare the priority levels of pending interrupt requests against each other, as well as to the current level of the processor. This is done in hardware. If the priority level of a pending interrupt is higher than others (including the current level of the processor), it will signal to the processor core and the processor will suspend current task and start processing the interrupt request as soon as possible.

regards,
Joseph
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