• Locked Locked
  • Replies 9 replies
  • Subscribers 119 subscribers
  • Views 6970 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Nested Interrupt CM3

Nino Caruso
Note: This was originally posted on 29th May 2012 at http://forums.arm.com

Hello everyone,
i just want to know how does nesting interrupt work on Cortex M3.
Register PRIMASK, BASEPRI and FAULTMASK are usefull if i want to ignore ,when occurs, certain interrupt (by setting a priority level threshold) ignore= interrup not accepted,  interrupt not nested
Register like SETENA enable or disable specific interrupt ( by # )
When the processor  is handling an exception and comes an interrupt that has upper priority level, the current exception is nested (save register etc etc ) and the new exception is executed. If the priority of the new interrupt is lower , the NVIC will not nest the interrupt, it will be ignored.

is correct what i've understood? is there something that i miss?



thank you in advance
Nino

ps i'm sorry for my bad english
Parents
  • Note: This was originally posted on 4th June 2012 at http://forums.arm.com

    -"In such case, the pending status of this interrupt will be set"
    in  particular : where the pendig status is set, for an internal interrupt  if the SETPEND is only for external interrupt?
    similarly for register SETENA/CLRENA, how can i enable/disable internal interrupt if the registers(SETENA,CLRENA) are associated only to  external interrupt?


    -How can the CM3 determine the priority of an internal interrupt that is programmable if there is not a priority level register associated to it?
    (ex: BUS FAULT exception #4 has a priority level programmable, where cm3 find it?)


    thank you in advance
Reply
  • Note: This was originally posted on 4th June 2012 at http://forums.arm.com

    -"In such case, the pending status of this interrupt will be set"
    in  particular : where the pendig status is set, for an internal interrupt  if the SETPEND is only for external interrupt?
    similarly for register SETENA/CLRENA, how can i enable/disable internal interrupt if the registers(SETENA,CLRENA) are associated only to  external interrupt?


    -How can the CM3 determine the priority of an internal interrupt that is programmable if there is not a priority level register associated to it?
    (ex: BUS FAULT exception #4 has a priority level programmable, where cm3 find it?)


    thank you in advance
Children
No data