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Nested Interrupt CM3

Nino Caruso
Note: This was originally posted on 29th May 2012 at http://forums.arm.com

Hello everyone,
i just want to know how does nesting interrupt work on Cortex M3.
Register PRIMASK, BASEPRI and FAULTMASK are usefull if i want to ignore ,when occurs, certain interrupt (by setting a priority level threshold) ignore= interrup not accepted,  interrupt not nested
Register like SETENA enable or disable specific interrupt ( by # )
When the processor  is handling an exception and comes an interrupt that has upper priority level, the current exception is nested (save register etc etc ) and the new exception is executed. If the priority of the new interrupt is lower , the NVIC will not nest the interrupt, it will be ignored.

is correct what i've understood? is there something that i miss?



thank you in advance
Nino

ps i'm sorry for my bad english
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  • Arm Employee Badge
    Note: This was originally posted on 30th May 2012 at http://forums.arm.com

    Hi Nino,

    The use of "ignore" is possibly not the best word.
    If an interrupt occurred, but:
    - the PRIMASK or FAULTMASK or BASEPRI is set, which result in blocking the interrupt, or
    - the Cortex-M3 is already running another interrupt handler with higher or same priority
    The processor will not accept the new interrupt.
    In such case, the pending status of this interrupt will be set, and the processor will process it later if:
    - the PRIMASK / FAULTMASK / BASEPRI is cleared, or
    - the processor finished the current executing Interrupt Service Routine (ISR) and exited the handler, which result in current priority level change.

    In overall, the interrupt request is not lost, but could be delayed by the interrupt masking registers or other interrupt services.

    regards,
    Joseph
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  • Arm Employee Badge
    Note: This was originally posted on 30th May 2012 at http://forums.arm.com

    Hi Nino,

    The use of "ignore" is possibly not the best word.
    If an interrupt occurred, but:
    - the PRIMASK or FAULTMASK or BASEPRI is set, which result in blocking the interrupt, or
    - the Cortex-M3 is already running another interrupt handler with higher or same priority
    The processor will not accept the new interrupt.
    In such case, the pending status of this interrupt will be set, and the processor will process it later if:
    - the PRIMASK / FAULTMASK / BASEPRI is cleared, or
    - the processor finished the current executing Interrupt Service Routine (ISR) and exited the handler, which result in current priority level change.

    In overall, the interrupt request is not lost, but could be delayed by the interrupt masking registers or other interrupt services.

    regards,
    Joseph
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