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Nested Interrupt CM3

Nino Caruso
Note: This was originally posted on 29th May 2012 at http://forums.arm.com

Hello everyone,
i just want to know how does nesting interrupt work on Cortex M3.
Register PRIMASK, BASEPRI and FAULTMASK are usefull if i want to ignore ,when occurs, certain interrupt (by setting a priority level threshold) ignore= interrup not accepted,  interrupt not nested
Register like SETENA enable or disable specific interrupt ( by # )
When the processor  is handling an exception and comes an interrupt that has upper priority level, the current exception is nested (save register etc etc ) and the new exception is executed. If the priority of the new interrupt is lower , the NVIC will not nest the interrupt, it will be ignored.

is correct what i've understood? is there something that i miss?



thank you in advance
Nino

ps i'm sorry for my bad english
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  • Arm Employee Badge
    Note: This was originally posted on 11th June 2012 at http://forums.arm.com

    Regarding WFI:

    >else if the interrupt will not be accepted due the priority it will not  wake up the processor, in this case it will be set as pending?

    Yes, correct.

    >is there a possibility that the interrupt wakeup the processor but will be set as pending?

    Yes, by setting PRIMASK.

    Regarding WFE:
    > Similar questions for WFE wakeup behavior, is there a possibility that a  event wakeup the processor but it will be set as pending?

    Yes, using the SEVONPEND feature. By setting bit 4 of System Control Register, an event is generate for a new pending of a interrupt, which can wake up the processor from WFE sleep.

    >  if yes,where is it set?  in the register SETPEND?

    Yes, in the pending status register. You can read back the current pending status from SETPEND (NVIC->ISPR) as well as CLRPEND (NVIC->ICPR).

    regards,
    Joseph
Reply
  • Arm Employee Badge
    Note: This was originally posted on 11th June 2012 at http://forums.arm.com

    Regarding WFI:

    >else if the interrupt will not be accepted due the priority it will not  wake up the processor, in this case it will be set as pending?

    Yes, correct.

    >is there a possibility that the interrupt wakeup the processor but will be set as pending?

    Yes, by setting PRIMASK.

    Regarding WFE:
    > Similar questions for WFE wakeup behavior, is there a possibility that a  event wakeup the processor but it will be set as pending?

    Yes, using the SEVONPEND feature. By setting bit 4 of System Control Register, an event is generate for a new pending of a interrupt, which can wake up the processor from WFE sleep.

    >  if yes,where is it set?  in the register SETPEND?

    Yes, in the pending status register. You can read back the current pending status from SETPEND (NVIC->ISPR) as well as CLRPEND (NVIC->ICPR).

    regards,
    Joseph
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