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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    SAU configuration failure 0

    • TrustZone for Armv8-M
    • Cortex-M33
    9162 views
    1 reply
    Latest over 6 years ago
    by Radhika Raghavendran
  • Suggested Answer

    Cortex M0 Vector Table and Bootloading 0

    • Cortex-M0
    • Interrupt Handling
    8873 views
    1 reply
    Latest over 6 years ago
    by Trampas
  • Answered

    Safe exit from HARD FAULT on CortexM0 +1

    • R15 (PC Program Counter)
    • Armv6-M
    • 3 (HardFault)
    14134 views
    9 replies
    Latest over 6 years ago
    by Trampas
  • Answered

    ARMv7M RefMan: What is "Rn" for "MVN"? +1

    • Registers
    • Armv7-M
    • Documentation
    • Thumb2
    3367 views
    2 replies
    Latest over 6 years ago
    by Niklas
  • Answered

    Regarding the J bit 0

    7092 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Rookie needs help +1

    3109 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    COrtex M7 cache hit rate measurement +1

    • Cortex-M7
    • performance
    • Cache Management
    4930 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    How to detect FPU in Cortex M? 0

    • Cortex-M
    4745 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Getting Execution Time of progams on armv8_64-bit processors +1

    • Cortex-A57
    • C++
    • Profiling
    • Armv8-A
    24390 views
    1 reply
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Answered

    About unsupported exclusive or atomic access issue +1

    25876 views
    2 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    DMA 0

    24244 views
    5 replies
    Latest over 6 years ago
    by Daniel72
  • Suggested Answer

    Secure SPI : STM32MP157-DK1 board 0

    • Armv7-A
    • stm32cubemx
    • Cortex-A
    • STM32
    • TrustZone
    23751 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    peripheral register access RMW vs Bit Banding 0

    5462 views
    4 replies
    Latest over 6 years ago
    by Lorenz Grübler
  • Answered

    What is the priority between synchronous data abort and FIQ in Cortex-R5F? 0

    • Cortex-R5
    • Interrupt
    9571 views
    6 replies
    Latest over 6 years ago
    by Etienne Alepins
  • Not Answered

    Obtain CPU Temperature in Kernel 0

    • Cortex-A53
    • Kernel Developers
    • Raspberry Pi 3
    • Armv8-A
    22515 views
    0 replies
    Started over 6 years ago
    by zzT
  • Answered

    How to initialize DCISW reg. +1

    21537 views
    1 reply
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Does "LDRD" instruction cause "UNDEFINSTR" error on Cortex-M4? 0

    • Cortex-M4
    11885 views
    9 replies
    Latest over 6 years ago
    by Gavin Li
  • Answered

    Cortex-M Vector Table and Address Remap 0

    • Embedded Software
    • Cortex-M0
    • Interrupt Handling
    • System on Chip (SoC)
    10587 views
    2 replies
    Latest over 6 years ago
    by eugch
  • Not Answered

    Detect if Interrupt Happened 0

    6172 views
    3 replies
    Latest over 6 years ago
    by Trampas
  • Answered

    Running two bare-metal programs on two separate cores in Cortex-A9 +1

    • Armv7-A
    • Cortex-A
    • DS-5 Debugger
    • Baremetal
    27908 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
<>
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