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Hi!
I'm getting hard fault error and I cannot figure out why. Can anybody point me to the right direction?
The architecture is Cortex-M4 with stack size of 0x3000.
It doesn't seem to be stack overflow as I raised it to the double size and still the hardfault ccurs. I triple checked the alignment of the protobuf array and it is seems ok. I'm not sure if there is a interrupt coming in but disabling all interrupt in the function doesn't seem to have any effect. What am I missing?
Thanks!
Indy
Processor status:
sp= 0x2001B1D0lr = 0xFFFFFFF1msp = 0x2001B1D0psp = 0x00000000
sp= 0x2001B1D0
lr = 0xFFFFFFF1
msp = 0x2001B1D0
psp = 0x00000000
R00 = 0x2001B1D0 R01 = 0x200101A0 R02 = 0x00000003 R03 = 0x200002C0 R04 = 0x00452B4A R05 = 0x200101A8 R06 = 0x2000453C R07 = 0x2001B210 R08 = 0x00000005 R09 = 0x00000005 R10 = 0x00447165 R11 = 0x2000A48C R12 = 0xFFFFFFFF
Here is the relevant code extrac failing at address 41dca6:
41dca6
c:
volatile static uint8_t protobuf[4096];
ASM:
41dc2c: b5f0 push {r4, r5, r6, r7, lr} 41dc2e: b099 sub sp, #100 ; 0x64 41dc30: af02 add r7, sp, #8 41dc32: 6078 str r0, [r7, #4] char* buf = (char*)protobuf; 41dc34: 4baa ldr r3, [pc, #680] ; (41dee0 <ws_handshake_open+0x2b4>) 41dc36: 64fb str r3, [r7, #76] ; 0x4c HALT_INVALID_SOCKET(socket); 41dc38: 687b ldr r3, [r7, #4] 41dc3a: 2b00 cmp r3, #0 41dc3c: db02 blt.n 41dc44 <ws_handshake_open+0x18> 41dc3e: 687b ldr r3, [r7, #4] 41dc40: 2b05 cmp r3, #5 41dc42: dd02 ble.n 41dc4a <ws_handshake_open+0x1e> 41dc44: f04f 33ff mov.w r3, #4294967295 41dc48: e1b3 b.n 41dfb2 <ws_handshake_open+0x386> buf[0] = '\0'; 41dc4a: 6cfb ldr r3, [r7, #76] ; 0x4c 41dc4c: 2200 movs r2, #0 41dc4e: 701a strb r2, [r3, #0] uri_set(s[socket].uri); 41dc50: 49a4 ldr r1, [pc, #656] ; (41dee4 <ws_handshake_open+0x2b8>) 41dc52: 687a ldr r2, [r7, #4] 41dc54: 4613 mov r3, r2 41dc56: 009b lsls r3, r3, #2 41dc58: 4413 add r3, r2 41dc5a: 00db lsls r3, r3, #3 41dc5c: 440b add r3, r1 41dc5e: 3320 adds r3, #32 41dc60: 681b ldr r3, [r3, #0] 41dc62: 4618 mov r0, r3 41dc64: 4ba0 ldr r3, [pc, #640] ; (41dee8 <ws_handshake_open+0x2bc>) 41dc66: 4798 blx r3 uri_get_host(host, sizeof(host)); 41dc68: f107 0308 add.w r3, r7, #8 41dc6c: 2140 movs r1, #64 ; 0x40 41dc6e: 4618 mov r0, r3 41dc70: 4b9e ldr r3, [pc, #632] ; (41deec <ws_handshake_open+0x2c0>) 41dc72: 4798 blx r3 strcat(buf, HTTP_GET" "); 41dc74: 6cf8 ldr r0, [r7, #76] ; 0x4c 41dc76: 4b9e ldr r3, [pc, #632] ; (41def0 <ws_handshake_open+0x2c4>) 41dc78: 4798 blx r3 41dc7a: 4603 mov r3, r0 41dc7c: 461a mov r2, r3 41dc7e: 6cfb ldr r3, [r7, #76] ; 0x4c 41dc80: 4413 add r3, r2 41dc82: 4a9c ldr r2, [pc, #624] ; (41def4 <ws_handshake_open+0x2c8>) 41dc84: 6810 ldr r0, [r2, #0] 41dc86: 6018 str r0, [r3, #0] 41dc88: 7912 ldrb r2, [r2, #4] 41dc8a: 711a strb r2, [r3, #4] reg = (uint32_t)buf; 41dc8c: 6cfb ldr r3, [r7, #76] ; 0x4c 41dc8e: 4a9a ldr r2, [pc, #616] ; (41def8 <ws_handshake_open+0x2cc>) 41dc90: 6013 str r3, [r2, #0] strcat(buf, "/ocpp?chargePointId="); 41dc92: 6cf8 ldr r0, [r7, #76] ; 0x4c 41dc94: 4b96 ldr r3, [pc, #600] ; (41def0 <ws_handshake_open+0x2c4>) 41dc96: 4798 blx r3 41dc98: 4603 mov r3, r0 41dc9a: 461a mov r2, r3 41dc9c: 6cfb ldr r3, [r7, #76] ; 0x4c 41dc9e: 4413 add r3, r2 41dca0: 4a96 ldr r2, [pc, #600] ; (41defc <ws_handshake_open+0x2d0>) 41dca2: 461d mov r5, r3 41dca4: 4614 mov r4, r2 ->41dca6: cc0f ldmia r4!, {r0, r1, r2, r3} 41dca8: 6028 str r0, [r5, #0] 41dcaa: 6069 str r1, [r5, #4] 41dcac: 60aa str r2, [r5, #8]
41dc2c: b5f0 push {r4, r5, r6, r7, lr}
41dc2e: b099 sub sp, #100 ; 0x64
41dc30: af02 add r7, sp, #8
41dc32: 6078 str r0, [r7, #4]
char* buf = (char*)protobuf;
41dc34: 4baa ldr r3, [pc, #680] ; (41dee0 <ws_handshake_open+0x2b4>)
41dc36: 64fb str r3, [r7, #76] ; 0x4c
HALT_INVALID_SOCKET(socket);
41dc38: 687b ldr r3, [r7, #4]
41dc3a: 2b00 cmp r3, #0
41dc3c: db02 blt.n 41dc44 <ws_handshake_open+0x18>
41dc3e: 687b ldr r3, [r7, #4]
41dc40: 2b05 cmp r3, #5
41dc42: dd02 ble.n 41dc4a <ws_handshake_open+0x1e>
41dc44: f04f 33ff mov.w r3, #4294967295
41dc48: e1b3 b.n 41dfb2 <ws_handshake_open+0x386>
buf[0] = '\0';
41dc4a: 6cfb ldr r3, [r7, #76] ; 0x4c
41dc4c: 2200 movs r2, #0
41dc4e: 701a strb r2, [r3, #0]
uri_set(s[socket].uri);
41dc50: 49a4 ldr r1, [pc, #656] ; (41dee4 <ws_handshake_open+0x2b8>)
41dc52: 687a ldr r2, [r7, #4]
41dc54: 4613 mov r3, r2
41dc56: 009b lsls r3, r3, #2
41dc58: 4413 add r3, r2
41dc5a: 00db lsls r3, r3, #3
41dc5c: 440b add r3, r1
41dc5e: 3320 adds r3, #32
41dc60: 681b ldr r3, [r3, #0]
41dc62: 4618 mov r0, r3
41dc64: 4ba0 ldr r3, [pc, #640] ; (41dee8 <ws_handshake_open+0x2bc>)
41dc66: 4798 blx r3
uri_get_host(host, sizeof(host));
41dc68: f107 0308 add.w r3, r7, #8
41dc6c: 2140 movs r1, #64 ; 0x40
41dc6e: 4618 mov r0, r3
41dc70: 4b9e ldr r3, [pc, #632] ; (41deec <ws_handshake_open+0x2c0>)
41dc72: 4798 blx r3
strcat(buf, HTTP_GET" ");
41dc74: 6cf8 ldr r0, [r7, #76] ; 0x4c
41dc76: 4b9e ldr r3, [pc, #632] ; (41def0 <ws_handshake_open+0x2c4>)
41dc78: 4798 blx r3
41dc7a: 4603 mov r3, r0
41dc7c: 461a mov r2, r3
41dc7e: 6cfb ldr r3, [r7, #76] ; 0x4c
41dc80: 4413 add r3, r2
41dc82: 4a9c ldr r2, [pc, #624] ; (41def4 <ws_handshake_open+0x2c8>)
41dc84: 6810 ldr r0, [r2, #0]
41dc86: 6018 str r0, [r3, #0]
41dc88: 7912 ldrb r2, [r2, #4]
41dc8a: 711a strb r2, [r3, #4]
reg = (uint32_t)buf;
41dc8c: 6cfb ldr r3, [r7, #76] ; 0x4c
41dc8e: 4a9a ldr r2, [pc, #616] ; (41def8 <ws_handshake_open+0x2cc>)
41dc90: 6013 str r3, [r2, #0]
strcat(buf, "/ocpp?chargePointId=");
41dc92: 6cf8 ldr r0, [r7, #76] ; 0x4c
41dc94: 4b96 ldr r3, [pc, #600] ; (41def0 <ws_handshake_open+0x2c4>)
41dc96: 4798 blx r3
41dc98: 4603 mov r3, r0
41dc9a: 461a mov r2, r3
41dc9c: 6cfb ldr r3, [r7, #76] ; 0x4c
41dc9e: 4413 add r3, r2
41dca0: 4a96 ldr r2, [pc, #600] ; (41defc <ws_handshake_open+0x2d0>)
41dca2: 461d mov r5, r3
41dca4: 4614 mov r4, r2
->41dca6: cc0f ldmia r4!, {r0, r1, r2, r3}
41dca8: 6028 str r0, [r5, #0]
41dcaa: 6069 str r1, [r5, #4]
41dcac: 60aa str r2, [r5, #8]
"ldmia r4!," ... reading longs from un-aligned ROM address.
From the Armv7-M manual:
The following data accesses always generate an alignment fault:• Non halfword-aligned LDREXH and STREXH.• Non word-aligned LDREX and STREX.• Non word-aligned LDRD, LDMIA, LDMDB, POP, LDC, VLDR, VLDM, and VPOP.• Non word-aligned STRD, STMIA, STMDB, PUSH, STC, VSTR, VSTM, and VPUSH.
Thanks Bastian!
I totally missed I was checking aligned buf and not the passed hard coded test string.
An additional question: is this gcc bug? How can I make sure that it always aligns the specific strings?
I can add -mno-unaligned-access gcc flag but I feel all the structs that are not aligned will be affected in my project.
Is there anyother way around this? Ideally, I'd have everything align at a function level.
There is __attribute__((align)) which might work.
Indy said:I'm getting hard fault error and I cannot figure out why
Suggest you get a copy of Joseph Yiu's Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors:
https://www.elsevier.com/books/the-definitive-guide-to-arm-cortex-m3-and-cortex-m4-processors/yiu/978-0-12-408082-9
It has a chapter on debugging Hard Faults ...