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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    What are the necessary preconditions to load a guest into EL1 from EL2? +1

    • EL1
    • EL2
    • ARMv8 Exception Model
    • Armv8-A
    • Hypervisor
    27095 views
    2 replies
    Latest over 5 years ago
    by MarekBykowski
  • Not Answered

    Cortex-A35 CoreMark results 0

    23056 views
    0 replies
    Started over 5 years ago
    by Etienne Alepins
  • Answered

    custom board based on cortex M0 toggle pins not responding. +1

    • Cortex-M0
    3475 views
    2 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Atomic write (LDAXR/STLXR) causes infinite loop on Cortex-A72 +1

    • Cortex-A72
    • AArch64
    24873 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Bootloader. VTOR, BOOTPROT FUSE, JUMP to app and other related questions +1

    • Cortex-M0
    • Cortex-M
    18828 views
    5 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    What is the top level difference in features between Cortex-M33 and Cortex-M4? 0

    • Cortex-M23
    • Trace
    • ACE
    • AXI
    • CHI
    • Security
    • Cortex-M3
    • Cortex-M
    • TrustZone
    • Cortex-M33
    • Armv8-M
    • Cortex-M4
    • Internet of Things (IoT)
    • AHB
    • Interrupt
    59326 views
    1 reply
    Latest over 6 years ago
    by bodybeacon
  • Answered

    Fail to connect with CM0DSEvel 0

    • Cortex-M0
    • DesignStart
    6142 views
    5 replies
    Latest over 6 years ago
    by RickyChen
  • Not Answered

    Use DS-5 MPS2_CM33 FVP in non-secure mode ? 0

    9022 views
    0 replies
    Started over 6 years ago
    by ilchang
  • Answered

    Cortex A9 core locks and cant't stop it +1

    • Debug Tools and Test Methods
    26828 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Suggested Answer

    Unable to Download Code to Controller 0

    • 5 (BusFault)
    • 3 (HardFault)
    • 6 (UsageFault)
    • Cortex-M4
    12044 views
    11 replies
    Latest over 6 years ago
    by Andy Neil
  • Answered

    How to set secondary core's registers from primary arm? 0

    • Cortex-A15
    • Cortex-A
    40708 views
    12 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"? +1

    • AArch64
    • Armv8-A
    • System MMU
    30338 views
    2 replies
    Latest over 6 years ago
    by Branden Sherrell
  • Answered

    NVIC_EnableIRQ : enables only one interrupt at a time? +1

    24964 views
    22 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Suggested Answer

    Emissivity value A72 0

    24565 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    SRAM reading problem using FMC at STM32H743. +1

    • Cortex-M7
    5223 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Answered

    Is return stack buffer implemented in Zync 7000 Soc +1

    • Cortex-A9
    • Branch Prediction
    23541 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    ARMv8 memory ordering +1

    • Cortex-A53
    • Armv8-A
    29466 views
    7 replies
    Latest over 6 years ago
    by a.surati
  • Answered

    Is there a built-in ARM assembly instruction for the following problem? +1

    • MDK-Arm
    • Arm Assembly Language (ASM)
    3361 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Answered

    Character recognition using NXP LPC1768 (Cortex-M3) +1

    • Neural Network
    • Cortex-M3
    • Arm NN
    6573 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Calling non-secure Reset Handler from Secure main 0

    • Cortex-M33
    • Armv8-M
    9077 views
    1 reply
    Latest over 6 years ago
    by Radhika Raghavendran
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Topics being discussed in this forum
  • AArch64
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  • Armv7-A
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