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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    SDRAM Window Boundary in MPU Address space in Cyclone V (Dual Cortex A9) 0

    • Cortex-A9
    22088 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    determine a page size on armv8 +1

    • Armv8-A
    • Memory Management Unit (MMU)
    24147 views
    2 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Suggested Answer

    How can I debug two A53 cores in DS-5 tool 0

    22133 views
    1 reply
    Latest over 6 years ago
    by Adeeljs
  • Not Answered

    Arm DynamIQ Shared Unit 0

    • L3
    • DynamIQ
    • Cache Architecture
    • DSU
    20427 views
    0 replies
    Started over 6 years ago
    by Errno
  • Not Answered

    ARM VETX.32 q1,q1,q1,#3 Slow 0

    19627 views
    0 replies
    Started over 6 years ago
    by br-dev
  • Answered

    Program Counter, Stack Pointer and Link Register Status During an Interrupt Service in ARM based Processors +1

    7326 views
    2 replies
    Latest over 6 years ago
    by Aman007kc
  • Answered

    ARM Assembly how to print numbers instead of their ascii representation of that number +1

    • Armv6
    • Arm Assembly Language (ASM)
    19111 views
    2 replies
    Latest over 6 years ago
    by Kanan Jarrus
  • Answered

    Cortex R8 axi unaligned transfer 0

    • program
    • cortex-r8
    5968 views
    2 replies
    Latest over 6 years ago
    by Ben Chen
  • Answered

    Nuvoton M2351 Keil RTX5 Hard faults on OS initialization 0

    • Cortex-M23
    • TrustZone for Armv8-M
    • Armv8-M
    5220 views
    2 replies
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Suggested Answer

    Best IDE to start with? 0

    5031 views
    1 reply
    Latest over 6 years ago
    by Trampas
  • Not Answered

    linked lists in lpc2136 error initializing pointers in null 0

    4614 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    EXC_RETURN when is floating point stack save? 0

    3900 views
    1 reply
    Latest over 6 years ago
    by Trampas
  • Not Answered

    Problem with Keil setup for NXP MKV 0

    2952 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    ARMv8-M MPS2_AEMv8M FVP, try to manually set XPSR in Privileged Secure state, the exception number cannot be set successfully. 0

    • AEMv8 FVP
    • Armv8-M
    2522 views
    0 replies
    Started over 6 years ago
    by Tao Lu
  • Not Answered

    Low-Level NOR Chip Interfacing and Embedded File System (EFS) Resources 0

    • Real Time Operating Systems (RTOS)
    • Timing
    • Keil Cortex-M Eval Boards
    • Clocking Structures & Timing Mechanisms
    • Keil MDK Professional Edition
    • Cortex-M4
    • CMSIS RTOS
    • Memory Devices
    • Memory
    2866 views
    0 replies
    Started over 6 years ago
    by japolo
  • Not Answered

    Runtime error when call a function from out of task 0

    2329 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    gnu toolchain for compiling Cortex-A code on my MAC os version 10.14. +1

    21589 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Question about program flow prediction 0

    • Cortex-A
    • Program Flow Trace Macrocell (PTM)
    19474 views
    0 replies
    Started over 6 years ago
    by alireza11048
  • Answered

    How to verify the Cortex-M0 thumb instructions ? I found one chip( RAM &FLASH is OK) when it run LDR relative instructions,the program is in Hardfault。But others run the same code is OK 0

    17373 views
    19 replies
    Latest over 6 years ago
    by hyue
  • Answered

    Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA? +1

    7337 views
    4 replies
    Latest over 6 years ago
    by RLA
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