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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    How vRestoreContextOfFirstTask works 0

    4758 views
    3 replies
    Latest over 5 years ago
    by Shibasis
  • Not Answered

    What if I set DISDEFWBUF and using MPU? 0

    3667 views
    2 replies
    Latest over 5 years ago
    by bigK
  • Not Answered

    Problem with frequency on STM32F103C8T6 0

    • Cortex-M3
    2570 views
    0 replies
    Started over 5 years ago
    by TechnoMan
  • Not Answered

    can i get cpu run state aarch64 or aarch32 fo cortex a57? 0

    24922 views
    3 replies
    Latest over 5 years ago
    by jhb
  • Not Answered

    Best way run driver code in privilege mode? 0

    6340 views
    7 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Raspberry pi with ARMV8.2 support 0

    • Raspberry Pi
    28031 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    interfacing m66 gsm module with stm32f0 +1

    4478 views
    2 replies
    Latest over 5 years ago
    by Rishabh_sharma
  • Not Answered

    which library should be used for half-precision mathematic functions? 0

    26401 views
    8 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex-M MPU User access to privileged code 0

    • Cortex-M
    • Memory Management
    5090 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Setting PC for and waking up secondary cores from the primary core +1

    • Armv8-A
    42762 views
    12 replies
    Latest over 5 years ago
    by jhoney
  • Not Answered

    How to generate an address size fault? 0

    4111 views
    0 replies
    Started over 5 years ago
    by ohskr27
  • Answered

    Unaligned accesses - CMSDK Example Cortex M0 0

    • Cortex-M0
    12461 views
    8 replies
    Latest over 5 years ago
    by eugch
  • Suggested Answer

    M7 data cache and Peripheral DMAs 0

    8919 views
    9 replies
    Latest over 5 years ago
    by Trampas
  • Answered

    Why ARM does not support 64bit for faulting address of IPA? +1

    • ARMv8 Exception Model
    • Armv8-A
    3486 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    uart cortex mo 0

    • Cortex-M0
    2681 views
    0 replies
    Started over 5 years ago
    by gnsh
  • Answered

    The code of app is freertos , the chip has a bootloader, The chip run on Cortex M0 +2

    4150 views
    2 replies
    Latest over 5 years ago
    by hyue
  • Answered

    Memory corruption in mov R4, 0; add R1, SP, #16; STB R4,[R1,#-1]! on Cortex-A9 with cache enabled, many interrupts EMAC, Timers after hours run. Not seeing in errata. R1 is not decremented and results corrupted stack data abort. Debugger not factor. +1

    28688 views
    5 replies
    Latest over 5 years ago
    by timholt
  • Suggested Answer

    Are there any Cortex-M controller with h.264 encoder? 0

    5099 views
    1 reply
    Latest over 5 years ago
    by Trampas
  • Answered

    Audio mixing efficiently and hard realtime requirment +1

    • algorithms
    • audio
    • Digital Signal Processor (DSP)
    • Cortex-M4
    • STM32 F4
    5079 views
    1 reply
    Latest over 5 years ago
    by Trampas
  • Answered

    How to remap the vector table location? The core of chip is cortex M0 +1

    3125 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
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