I have this 'tight' piece of ASM I'm looking at how it's working, and it contains IT instruction ( I've never seen before until now).
Now all code works (compiler generated!) , but, i'm also stepping though each instruction for cycle counting, and , in this IT block I see that, firstly seems I step through every instruction always - no matter the data/numbers - and, by CM4 cycle counter is always bumped , so I presume instruction then following IT is always executed (even logically it shouldn't )
Can someone shine a light for me :
0100093a: 4291 cmp r1, r2 0100093c: BF28 it hs 0100093e: 4611 mov r1, r2
So just so you understand : r1 and r2 may have different numbers, and in fact can always be different and one less than other. So I would expect that, after "it hs", the "mov" is conditional - that if condition not true, it will be skipped , and definitely no cycles for "mov" added.
But ... this is not what I see in my debugger . Help me understand please? Seems i go through all these instructions _always_ independent of data.
Is this something like this :
the instruction(s) in IT block following IT go through pipeline including exec stage, but in the end exec outcome depends on the status bits set by "cmp".Err, don't fully see this, but somehow, in the exec of "mov" the actual transfer to another register is conditional.
The cool thing about this IT block is , if I understand, no branch/jump, and always same number of cycles independent of actual result of the condition.
Please correct me .. ?