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I'm checking cycles with DWT while single stepping instructions. I have the following piece :
110 *minp = min; 0100094c: F8C91000 str.w r1, [r9] 111 *maxp = max; 01000950: F8C80000 str.w r0, [r8]
Above & below them, there is no other immediate stores
Now, the cycle counter tells me 1 cycle per each of those "str.w", and with reference:http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/CHDDIGAC.html
.. note [b]: "Neighboring load and store single instructions can pipeline their address and data phases. This enables these instructions to complete in a single execution cycle."
So this must be, what I see ? (otherwise I would have at least 2 cycles..) . But how does this work, shouldn't the first str.w instruction be 2 cycles, but the immediately following one(s) 1 cycle ?
If someone could explain this would be awesome.