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EDSCR err bit set after a write to EDITR

kka

Hi,

I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".

So I try to follow that to give the state information.

Cortex-57

JTAG TCK = 3,788MHz.

ARM_STATE_AARCH64 is set

Before Halt state:

EDPRSR = 0x1

EDSCR = 0x03007C02

After Halt state:

EDPRSR = 0x1

EDSCR = 0x03006113

After Write to EDITR with opcode 0xd503201f for a NOP instruction:

EDPRSR = 0x11

EDSCR = 0x03006153

EDSCR differs from the resolved entry in bits HDE=1, RW=0100, EL=1

And Aarch64 has no thumb mode instruction, this does not solve my problem.

Any help is appreciated.

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  • 0 in reply to Stuart Hirons

    Ok, as you have said, here the initialization is missing some lines, which are relevant for resuming the PC, which are there in openOCD. But other than that the only difference was CTI unlock and this did not help with the problem either.

    My DBGAUTHSTATUS_EL1 register reads 0x000000FF, which I understand, that everything should be enabled.

Reply
  • 0 in reply to Stuart Hirons

    Ok, as you have said, here the initialization is missing some lines, which are relevant for resuming the PC, which are there in openOCD. But other than that the only difference was CTI unlock and this did not help with the problem either.

    My DBGAUTHSTATUS_EL1 register reads 0x000000FF, which I understand, that everything should be enabled.

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