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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Answered

    CSAL on ARM A9 0

    20949 views
    4 replies
    Latest over 5 years ago
    by Kalindu
  • Not Answered

    multi os arm cortex 0

    4212 views
    4 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    ARM A64 Page table 0

    • Cortex-A72
    • AArch64
    • virtualization
    • Memory Management Unit (MMU)
    18925 views
    0 replies
    Started over 5 years ago
    by venmer
  • Answered

    Protection control 0

    20668 views
    3 replies
    Latest over 5 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    Where can I find the sc300 Technical reference manual? 0

    5007 views
    2 replies
    Latest over 5 years ago
    by YimoYimo
  • Answered

    Best way to safely check if virtual address exists 0

    22368 views
    4 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Is it necessary to flush data cache of a modified page table entry? 0

    • Memory Management Unit (MMU)
    21487 views
    1 reply
    Latest over 5 years ago
    by astonelin@gmail.com
  • Answered

    Old startup .s files from DS-1, etc. 0

    19626 views
    2 replies
    Latest over 5 years ago
    by smblackledge
  • Answered

    cortex m4 IP 0

    4419 views
    5 replies
    Latest over 5 years ago
    by Andy Neil
  • Answered

    can we delay read and write transactions(axi4) by providing delay in register slice? 0

    • AXI4
    124789 views
    67 replies
    Latest over 5 years ago
    by casseverhart13
  • Not Answered

    MPU config and memory attributes 0

    • Cortex-M7
    • STM32
    • STM32 F7
    8662 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Transition from EL3 to EL1 on A53 0

    20423 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex-A35 cache partitioning 0

    • Cache
    • Cache Management
    • Cache Architecture
    19605 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Bare Metal I/O documentation help 0

    18905 views
    3 replies
    Latest over 5 years ago
    by Andy Neil
  • Answered

    Transmitting and reconstructing DSP data over internet. 0

    5548 views
    6 replies
    Latest over 5 years ago
    by Phalelashvili
  • Not Answered

    Cycle accurate Cortex-M3 simulator using obsfucated RTL 0

    • Cycle Models
    • Cortex-M3
    • Hardware Modelling/Simulation
    5201 views
    2 replies
    Latest over 5 years ago
    by TinyLabs
  • Not Answered

    vldr d16, [r7, #200] ; 0xc8 causes Hard fault (Forced) 0

    4693 views
    1 reply
    Latest over 5 years ago
    by chrisc11
  • Not Answered

    How to change CM33 State from secure to non-secure 0

    • TrustZone for Armv8-M
    • Cortex-M33
    4932 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Memory related issue with MCU startup ( __libc_init_array ) +1

    • Toolchain
    • Cortex-M
    • stm32l4
    27280 views
    8 replies
    Latest over 5 years ago
    by Jacob Beningo
  • Not Answered

    STM32H7 CAN FD issues 0

    • Cortex-M7
    • stm32 h7
    • Keil
    10342 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
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  • AXI
  • Cache
  • Cortex-A
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  • Cortex-A7
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  • Cortex-M0
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