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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3620 Questions
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  • Answered

    A35 Power Mode Transitions 0

    22715 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Regarding the documentation on the T1 encoding of the MOV instruction on ARMv6-M architecture 0

    • Armv6-M
    • Documentation
    6098 views
    3 replies
    Latest over 6 years ago
    by B. Robertson
  • Answered

    Why does Arm still support short descriptors? +1

    • Armv7-A
    • Armv8-A
    • Memory Management Unit (MMU)
    21063 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Answered

    In Arm v7 mmu, stage2 translation cannot use short descriptors. WHY? +1

    • EL1
    • Armv7-A
    • EL0
    • Memory Management Unit (MMU)
    • Hypervisor
    28207 views
    3 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    BURST option in AHB-to-AHB sync-up bridge 0

    21751 views
    2 replies
    Latest over 6 years ago
    by misimovi
  • Answered

    Processor halt in __libc_init_array assembler function 0

    25516 views
    8 replies
    Latest over 6 years ago
    by Andy Neil
  • Suggested Answer

    adc read 0

    • Cortex-M0
    3983 views
    2 replies
    Latest over 6 years ago
    by Andy Neil
  • Answered

    How to access memory more than 4GB by using 32bit ISA? +1

    • Memory Access Instructions
    7811 views
    4 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Saving processor state for power-down and resume 0

    • Thumb
    • Cortex-M4
    4864 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Pros and cons of activating cache in stm32F7 0

    4185 views
    0 replies
    Started over 6 years ago
    by Marzi
  • Not Answered

    making physical memory pages not cacheable (probabaly by modifying page table entry) 0

    20569 views
    0 replies
    Started over 6 years ago
    by Gol
  • Not Answered

    Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore 0

    • System on Chip (SoC)
    • Cortex-A9
    22439 views
    3 replies
    Latest over 6 years ago
    by BurakSeker
  • Not Answered

    flush_cache_all() API consuming 200+ microseconds. 0

    21512 views
    4 replies
    Latest over 6 years ago
    by vaiyawa
  • Answered

    R5 vs A9 Performances +1

    • Cortex-A9
    • Cortex-R5
    13518 views
    9 replies
    Latest over 6 years ago
    by Poz1
  • Suggested Answer

    Where can I apply for cortex m0/m3 IP with GDSII files 0

    3101 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Is it typical at least 2 cycles taken for load from and store to a zero wait state accessible memory? 0

    • Memory Access Instructions
    4594 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Address memory of the next instruction in A9 MPCore 0

    • R15 (PC Program Counter)
    21901 views
    3 replies
    Latest over 6 years ago
    by dVaquerizo
  • Answered

    How to flush write buffer when memory attribute is normal_nc 0

    • Cache coherency
    26671 views
    4 replies
    Latest over 6 years ago
    by bamvor2022
  • Answered

    ARM R5 and A53 cores coexist +1

    27084 views
    2 replies
    Latest over 6 years ago
    by Stuart Hirons Arm Employee Badge
  • Not Answered

    Hard fault : Cortex M0+ platform. 0

    • Cortex-M0+
    4937 views
    4 replies
    Latest over 6 years ago
    by Tejeshwar
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