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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Not Answered

    How to test L1/L2 cache? 0

    15554 views
    2 replies
    Latest over 5 years ago
    by Zhiping Jiang
  • Not Answered

    Which bit fields are for Cortex-M4F SCB_ICSR.VECTORPENDING 0

    • Cortex-M4
    2883 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Tasks can't switch to others, always run at OSStartHang. but whitout boot code ,the app can run ok. the core of the chip is cortex-M0 +2

    8048 views
    7 replies
    Latest over 5 years ago
    by John_shi
  • Answered

    Speculative execution/loads on Cortex-A5 0

    • Cortex-A5
    • Pipeline Control and Execution
    • Cache
    16111 views
    5 replies
    Latest over 5 years ago
    by vstehle Arm Employee Badge
  • Answered

    Direct Virtual Interrupts (Timer Interrupt and IPI ) +1

    11352 views
    1 reply
    Latest over 5 years ago
    by vstehle Arm Employee Badge
  • Answered

    Inconsistent shareability domain on tlbi instructions 0

    • Cortex-A72
    • Cortex-A53
    14880 views
    3 replies
    Latest over 5 years ago
    by josecm
  • Not Answered

    Memory violation calling ATSAM3X8 0

    1576 views
    0 replies
    Started over 5 years ago
    by ccandido
  • Not Answered

    Instruction Count and Memory Access 0

    • CoreSight Debug and Trace
    • Musca-A
    • Cortex-M33
    4884 views
    2 replies
    Latest over 5 years ago
    by Lica
  • Answered

    Understanding interrupt latency and jitter in Cortex-M 0

    • Interrupt Handling
    • Cortex-M7
    • Cortex-M
    • Interrupt
    12709 views
    7 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Suggested Answer

    ARM M0 and M3 0

    2824 views
    2 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Problems with DSP course 0

    1383 views
    0 replies
    Started over 5 years ago
    by goldenthyme
  • Answered

    ID issue 0

    13170 views
    2 replies
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Use keil5 to compile AM335X +1

    12986 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Suggested Answer

    How many clock cycles does a"for" loop take? 0

    13449 views
    5 replies
    Latest over 5 years ago
    by WestfW
  • Answered

    DWT instruction address 0

    • CoreSight Debug and Trace
    • Cortex-M33
    • Armv8-M
    3663 views
    2 replies
    Latest over 5 years ago
    by Lica
  • Not Answered

    cortex M33 multicore debug resources 0

    2818 views
    3 replies
    Latest over 5 years ago
    by Sinie
  • Not Answered

    Reading Non-Secure PENDSVSET after re-entry into Secure PendSV 0

    2949 views
    2 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    About the snoop filter in CCI 550 0

    • Cache coherency
    • CoreLink CCI-550 Cache Coherent Interconnect
    13283 views
    0 replies
    Started over 5 years ago
    by zilly
  • Answered

    Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache? 0

    • Cortex-A53
    • Cache
    • Cortex-A
    22375 views
    4 replies
    Latest over 5 years ago
    by zilly
  • Not Answered

    DRAM address mapping on a Cortex-A72 ARMv8 0

    • Cortex-A72
    • Armv8-A
    13568 views
    2 replies
    Latest over 5 years ago
    by Frederick
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