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why there are separate registers for interrupt set-enable and clear-enable while can be just one

Morteza

I can't understand why there are separate registers like Interrupt Set-Enable and Clear-Enable Registers or Interrupt Set-Pending and Clear-Pending Register in NVIC? these dual registers couldn't be handled in just one? what are the reasons that ARM processors separate them in different registers?

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  • 0 in reply to Andy Neil

    Thanks! I get it. It's a really interesting trick.

    In the arm processor implementation, there is just one register for Pending and the rest are connected to set/clear of the FF or three separate registers (Set-Enable, Clear-Enable, and Pending)?

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  • 0 in reply to Andy Neil

    Thanks! I get it. It's a really interesting trick.

    In the arm processor implementation, there is just one register for Pending and the rest are connected to set/clear of the FF or three separate registers (Set-Enable, Clear-Enable, and Pending)?

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