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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Answered

    Where to start with ARM Trust-zone development for Cortex-A series? +1

    16135 views
    6 replies
    Latest over 4 years ago
    by br-dev
  • Not Answered

    Ecc error injection on Iram1 of Cortex-R5f 0

    2800 views
    2 replies
    Latest over 4 years ago
    by rambohuang
  • Not Answered

    Are the IDAU NS and NSC signals assumed to be mutually exclusive? 0

    2482 views
    0 replies
    Started over 4 years ago
    by kappajacko
  • Answered

    Cortex M0/M0+/M1 32-bit x 32-bit --->64-bit signed multiply +1

    • Cortex-M0
    • Cortex-M1
    • Cortex-M
    18249 views
    9 replies
    Latest over 4 years ago
    by Sean Dunlevy
  • Answered

    TLB coherence expectation with TF-A running on ARM Neoverse N1 cores and CMN-600 network +1

    5900 views
    6 replies
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Microcontroller selection - Requirements and question in description 0

    • 32-bit
    • Bluetooth
    • PL351 NAND Flash Memory Controller
    • Microcontroller (MCU)
    • bluetooth 5
    • Cortex-M
    • Bluetooth LE
    • dram
    2334 views
    1 reply
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Cortex R5 Application Execution 0

    1948 views
    1 reply
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Are there any moderators to wipe out the spam? +1

    4143 views
    3 replies
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Maybe a bug in the CMSIS library. 0

    2558 views
    6 replies
    Latest over 4 years ago
    by Andy Neil
  • Answered

    32-bit x 32-bit --->64-bit multiply +1

    • Cortex-M0
    • Cortex-M0+
    • Arm Assembly Language (ASM)
    5756 views
    5 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    SAU vs. IDAU in a System with Multiple Masters 0

    • Security
    • TrustZone
    • Armv8-M
    16426 views
    5 replies
    Latest over 4 years ago
    by Chris Reed Arm Employee Badge
  • Not Answered

    Debug single step and interrupts not executing 0

    • Interrupt Handling
    • 14 (PendSV)
    • Debugging
    • Cortex-M4
    2157 views
    0 replies
    Started over 4 years ago
    by KjO
  • Suggested Answer

    Where can I find "ARMv8 Instruction Set Overview" (PRD03-GENC-010197) 0

    • AArch64
    • Armv8-A
    6583 views
    7 replies
    Latest over 4 years ago
    by Senna van Hoek
  • Suggested Answer

    Arm Musca A1 - SRAM0 MPC Security attribute during boot 0

    • Musca-A
    • TrustZone for Armv8-M
    • CoreLink SSE-200
    6022 views
    2 replies
    Latest over 4 years ago
    by Daniel Oliveira
  • Answered

    MRAM Data Losing Problem 0

    3576 views
    5 replies
    Latest over 4 years ago
    by Andy Neil
  • Answered

    8051 cannot get serial port 1 to work +2

    • Keil C51 Dev Tools
    • C
    6895 views
    3 replies
    Latest over 4 years ago
    by Birmingham
  • Not Answered

    Cortex-M3 r2p1 TRM Document CPUID.PARTNO is wrong? 0

    1939 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    ARM Core M0 as test chip 0

    1212 views
    0 replies
    Started over 4 years ago
    by pranjal_100
  • Not Answered

    how to write interrupts function for STM32f103 in Keil 0

    2435 views
    1 reply
    Latest over 4 years ago
    by Robert McNamara
  • Answered

    Processor always jumps to default exception handler 0

    • Interrupt Handling
    • Cortex-M4
    11711 views
    13 replies
    Latest over 4 years ago
    by WestfW
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