1. I READ the cortex-a78 trm, i confuse with the L1 Cache, what is VIPT behaves as PIPT? if L1 Cache is VIPT, Can it be understood as On a memory access operation, core get the physical addresses from L1 Cache first, if it do not hit ,than find the MMU?
2. what is the cache means? is it a contains L1 L2 L3 cache?
It means that software can handle the cache as PIPT, the cache micro architecture would solve the cache alias issue.
Why not use PIPT directly？
In Intel CPUs, the VIPT L1 caches have all the index bits from the offset-within-page part of the address, so virt=phys, avoiding any aliasing problems. ... The full physical address is known just from L1d index + tag, again because it behaves like a PIPT for everything except load latency.
JCPenney Kiosk
thanks, when the cache size is big than page size; i found i can use page coloring to resolve;
i found Page-based hardware attributes(PBHA) in MMU in the cortex-a78 trm, does it can solve this problem?
No PBHA is not relevant to VIPT or PIPT, it is an CPU implementation defined behavior for system usage, which is decided by SoC designer
thanks very much