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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    boot config Stm32g0 0

    3322 views
    3 replies
    Latest over 4 years ago
    by Alejandran
  • Suggested Answer

    Cortex 8.2A : FEAT_SHA3 0

    6463 views
    9 replies
    Latest over 4 years ago
    by br-dev
  • Not Answered

    Does E0PD mechanism provide Meltdown mitigation? 0

    20395 views
    1 reply
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    why output of rndr instruction is mixed with bootloader's entropy to form linux kaslr on arm64 0

    • Armv8-A
    4294 views
    3 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    Fault Handler for ARM Cortex-A Series on Beaglebone Black 0

    • BeagleBone Black
    • Cortex-A8
    3237 views
    2 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    External Private Peripheral Bus +1

    • CoreSight Architecture
    • Cortex-M
    • Debugging
    3030 views
    1 reply
    Latest over 4 years ago
    by Haiyan Arm Employee Badge
  • Not Answered

    Debug Armv8-A alternative in ARM DS 0

    • Armv8-A
    • Armv8 Foundation Platform
    4291 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Accessing Arm cortex M3 processor inside FPGA using xilinx JTAG 0

    3195 views
    2 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    how to understand multi-copy atomicity and who is in charge to maintain this property 0

    • Armv8-A
    9650 views
    6 replies
    Latest over 4 years ago
    by summer123
  • Not Answered

    Are 128 bits atomic accesses possible with Cortex-A35? 0

    • Cortex-A35
    • 128-bit
    3960 views
    3 replies
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    recovery from illegal instruction Undef Abort exception 0

    3044 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex M7 cache ECC error 0

    • Cortex-M7
    3449 views
    1 reply
    Latest over 4 years ago
    by Robert McNamara
  • Not Answered

    Record trace on-chip with ETM on STM32H7 (Cortex M7) 0

    • stm32 h7
    • CoreSight ETM-M7
    2321 views
    0 replies
    Started over 4 years ago
    by GuillaumeP
  • Answered

    The Monitor 0

    • TrustZone
    9757 views
    4 replies
    Latest over 4 years ago
    by yufeifei
  • Not Answered

    Patent of ARM's single-cycle multiply on the M0+? 0

    3401 views
    6 replies
    Latest over 4 years ago
    by Sean Dunlevy
  • Not Answered

    Data Cache Zero by Virtual Address (DC ZVA) instruction 0

    • Armv8-A
    • Cortex-A73
    7793 views
    1 reply
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Answered

    Accessing GIC registers 0

    • CoreLink GIC-400 Generic Interrupt Controller
    • Interrupt Handling
    • AArch64
    5616 views
    3 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    Cross-compiling Arm NN for the Raspberry Pi and TensorFlow issue 0

    2296 views
    0 replies
    Started over 4 years ago
    by Huy
  • Answered

    Cortex-A53 - Understanding Translation Table (Cannot enable MMU) +1

    • Cortex-A53
    • Memory Management Unit (MMU)
    5250 views
    1 reply
    Latest over 4 years ago
    by krjdev
  • Suggested Answer

    α version of second pass DCT for MP3 decoder on M0/M0+ & THAT Multiply issue 0

    4029 views
    6 replies
    Latest over 4 years ago
    by Sean Dunlevy
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