We use a system based on OpenAmp with Linux running on CPU0 (L1+L2 cache) and FreeRTOS on CPU1 (only L1 cache).
I'm a bit in doubt regarding MMU table configuration on CPU1.
The shared bit enables cache coherency between L1 caches and L2 cache. We don't use this.
We see the DDR as single point of truth for shared data (small volume, preprocessed on CPU1 side or provided via IP cores / DMA) and notify the other system after flushing the cache.
Are these setting correct to have CPU1 isolated from all coherency mechanisms?
Tex 2:0 C B
000 0 0 - Strongly ordered (peripherals)
001 0 0 - Non cached memory
100 c1 b1 - Cached memory (L1 cache only)
Are you sure you can limit L2 to CPU0 only? I am not.
The L2 cache is physically active (enabled by CPU0).
But with the above settings (TEX:100) I would expect that the L2 cache doesn't come into affect for CPU1. The L2 cache controller should bypass all accesses directly to DDR, shouldn't it? Or do I miss something here? We're using a Zynq 7000 and the cache maintenance functions provided by Xilinx' framework don't touch L2, only L1.
In this case, you might not set ACTLR.SMP bit.
Signals if the Cortex-A9 processor is taking part in coherency or not.
In uniprocessor configurations, if this bit is set, then Inner Cacheable Shared is treated as Cacheable. The reset value is zero.
If the SMP bit is not set for the CPU, then the CPU would not take part in coherency.
and since linux kernel is running on one CPU only, you might set CONFIG_SMP =n
PL310 L2 cache supports cache lockdown for one CPU.
Thanks, thats an interesting option.
When I said cache lockdown, it means that some L2 cache ways could be configured in a way that the cache way can only perform cache allocation for one CPU's access. But the allocated cache can still be accessed by other CPUs.